dds_top.map.rpt

实现数字频率合成。能产生任意频率的正弦信号、方波信号、梯形波等

Analysis & Synthesis report for dds_top
Thu Mar 06 14:45:06 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Parameter Settings for User Entity Instance: 48:inst4|74161:inst1
 11. Parameter Settings for User Entity Instance: 48:inst4|74161:inst
 12. Parameter Settings for User Entity Instance: 1hz1khz:inst3|fenpin:inst2|74161:inst2
 13. Parameter Settings for User Entity Instance: 1hz1khz:inst3|fenpin:inst2|74161:inst1
 14. Parameter Settings for User Entity Instance: 1hz1khz:inst3|fenpin:inst2|74161:inst
 15. Parameter Settings for User Entity Instance: 1hz1khz:inst3|fenpin:inst3|74161:inst2
 16. Parameter Settings for User Entity Instance: 1hz1khz:inst3|fenpin:inst3|74161:inst1
 17. Parameter Settings for User Entity Instance: 1hz1khz:inst3|fenpin:inst3|74161:inst
 18. Parameter Settings for User Entity Instance: 1hz1khz:inst3|48:inst|74161:inst1
 19. Parameter Settings for User Entity Instance: 1hz1khz:inst3|48:inst|74161:inst
 20. Parameter Settings for User Entity Instance: 24x4:inst18|74151:inst
 21. Parameter Settings for User Entity Instance: 24x4:inst18|74151:inst1
 22. Parameter Settings for User Entity Instance: 24x4:inst18|74151:inst2
 23. Parameter Settings for User Entity Instance: 24x4:inst18|74151:inst3
 24. Parameter Settings for User Entity Instance: cepin:inst9|24x4:inst13|74151:inst
 25. Parameter Settings for User Entity Instance: cepin:inst9|24x4:inst13|74151:inst1
 26. Parameter Settings for User Entity Instance: cepin:inst9|24x4:inst13|74151:inst2
 27. Parameter Settings for User Entity Instance: cepin:inst9|24x4:inst13|74151:inst3
 28. Parameter Settings for User Entity Instance: Sine_rom:inst7|altsyncram:altsyncram_component
 29. Parameter Settings for User Entity Instance: kuopx161:inst16|74161:inst
 30. Parameter Settings for User Entity Instance: kuopx161:inst16|74161:inst1
 31. Parameter Settings for User Entity Instance: kuopx161:inst15|74161:inst
 32. Parameter Settings for User Entity Instance: kuopx161:inst15|74161:inst1
 33. Parameter Settings for User Entity Instance: two_rom:inst33|altsyncram:altsyncram_component
 34. Analysis & Synthesis Equations
 35. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Mar 06 14:45:05 2008    ;
; Quartus II Version          ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name               ; dds_top                                  ;
; Top-level Entity Name       ; dds                                      ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 309                                      ;
; Total pins                  ; 44                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 81,920                                   ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C12Q240C8 ;               ;
; Top-level entity name                                              ; dds          ; dds_top       ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Use smart compilation                                              ; Off          ; Off           ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;