dds_top.tan.rpt

来自「实现数字频率合成。能产生任意频率的正弦信号、方波信号、梯形波等」· RPT 代码 · 共 254 行 · 第 1/5 页

; Worst-case tpd               ; N/A                                      ; None          ; 17.197 ns                                      ; key7                       ; bb                                                                                                            ;            ;          ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; -3.193 ns                                      ; key1                       ; kuopx161:inst15|74161:inst1|f74161:sub|110                                                                    ;            ; cpp0     ; 0            ;
; Clock Setup: '48mhz'         ; N/A                                      ; None          ; 114.04 MHz ( period = 8.769 ns )               ; 8jcq:inst8|74175:inst|15   ; Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|ram_block1a9~porta_address_reg10 ; 48mhz      ; 48mhz    ; 0            ;
; Clock Setup: 'cpx0'          ; N/A                                      ; None          ; 175.47 MHz ( period = 5.699 ns )               ; kuopx:inst14|74160:inst1|6 ; kuopx:inst14|74160:inst4|7                                                                                    ; cpx0       ; cpx0     ; 0            ;
; Clock Setup: 'cpp0'          ; N/A                                      ; None          ; 198.93 MHz ( period = 5.027 ns )               ; kuopx:inst19|74160:inst1|6 ; kuopx:inst19|74160:inst4|7                                                                                    ; cpp0       ; cpp0     ; 0            ;
; Clock Setup: 'key8'          ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 3:inst36|74160:inst|7      ; 3:inst36|74160:inst|6                                                                                         ; key8       ; key8     ; 0            ;
; Clock Hold: '48mhz'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; cepin:inst9|74160:inst3|6  ; cepin:inst9|74175:inst8|16                                                                                    ; 48mhz      ; 48mhz    ; 20           ;
; Total number of failed paths ;                                          ;               ;                                                ;                            ;                                                                                                               ;            ;          ; 20           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+----------------------------+---------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; 48mhz           ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; cpp0            ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; cpx0            ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; key8            ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: '48mhz'                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+