dds_top.fit.eqn

实现数字频率合成。能产生任意频率的正弦信号、方波信号、梯形波等

--operation mode is normal

AB61_14 = DFFEAS(Y1_inst4, A1L12, cl, , , AB1_14, , , VCC);


--LB1_q_a[1] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[1] at M4K_X19_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[1]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[1]_PORT_A_address_reg = DFFE(LB1_q_a[1]_PORT_A_address, LB1_q_a[1]_clock_0, , , );
LB1_q_a[1]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[1]_PORT_A_data_out = MEMORY(, , LB1_q_a[1]_PORT_A_address_reg, , , , , , LB1_q_a[1]_clock_0, , , , , );
LB1_q_a[1]_PORT_A_data_out_reg = DFFE(LB1_q_a[1]_PORT_A_data_out, LB1_q_a[1]_clock_0, , , );
LB1_q_a[1] = LB1_q_a[1]_PORT_A_data_out_reg[0];


--Y1_inst3 is 9or:inst42|inst3 at LC_X26_Y10_N5
--operation mode is normal

AB61_15_qfbk = AB61_15;
Y1_inst3 = AB61_15_qfbk # LB1_q_a[1];

--AB61_15 is 10jcq_zong:inst41|74175:inst|15 at LC_X26_Y10_N5
--operation mode is normal

AB61_15 = DFFEAS(Y1_inst3, A1L12, cl, , , AB1_15, , , VCC);


--LB1_q_a[0] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[0] at M4K_X19_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[0]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[0]_PORT_A_address_reg = DFFE(LB1_q_a[0]_PORT_A_address, LB1_q_a[0]_clock_0, , , );
LB1_q_a[0]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[0]_PORT_A_data_out = MEMORY(, , LB1_q_a[0]_PORT_A_address_reg, , , , , , LB1_q_a[0]_clock_0, , , , , );
LB1_q_a[0]_PORT_A_data_out_reg = DFFE(LB1_q_a[0]_PORT_A_data_out, LB1_q_a[0]_clock_0, , , );
LB1_q_a[0] = LB1_q_a[0]_PORT_A_data_out_reg[0];


--Y1_inst is 9or:inst42|inst at LC_X26_Y10_N4
--operation mode is normal

AB61_16_qfbk = AB61_16;
Y1_inst = AB61_16_qfbk # LB1_q_a[0];

--AB61_16 is 10jcq_zong:inst41|74175:inst|16 at LC_X26_Y10_N4
--operation mode is normal

AB61_16 = DFFEAS(Y1_inst, A1L12, cl, , , AB1_16, , , VCC);


--GB1_q_a[9] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[9] at M4K_X19_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[9]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[9]_PORT_A_address_reg = DFFE(GB1_q_a[9]_PORT_A_address, GB1_q_a[9]_clock_0, , , );
GB1_q_a[9]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[9]_PORT_A_data_out = MEMORY(, , GB1_q_a[9]_PORT_A_address_reg, , , , , , GB1_q_a[9]_clock_0, , , , , );
GB1_q_a[9]_PORT_A_data_out_reg = DFFE(GB1_q_a[9]_PORT_A_data_out, GB1_q_a[9]_clock_0, , , );
GB1_q_a[9] = GB1_q_a[9]_PORT_A_data_out_reg[0];


--GB1_q_a[8] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[8] at M4K_X19_Y9
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[8]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[8]_PORT_A_address_reg = DFFE(GB1_q_a[8]_PORT_A_address, GB1_q_a[8]_clock_0, , , );
GB1_q_a[8]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[8]_PORT_A_data_out = MEMORY(, , GB1_q_a[8]_PORT_A_address_reg, , , , , , GB1_q_a[8]_clock_0, , , , , );
GB1_q_a[8]_PORT_A_data_out_reg = DFFE(GB1_q_a[8]_PORT_A_data_out, GB1_q_a[8]_clock_0, , , );
GB1_q_a[8] = GB1_q_a[8]_PORT_A_data_out_reg[0];


--GB1_q_a[7] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[7] at M4K_X19_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[7]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[7]_PORT_A_address_reg = DFFE(GB1_q_a[7]_PORT_A_address, GB1_q_a[7]_clock_0, , , );
GB1_q_a[7]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[7]_PORT_A_data_out = MEMORY(, , GB1_q_a[7]_PORT_A_address_reg, , , , , , GB1_q_a[7]_clock_0, , , , , );
GB1_q_a[7]_PORT_A_data_out_reg = DFFE(GB1_q_a[7]_PORT_A_data_out, GB1_q_a[7]_clock_0, , , );
GB1_q_a[7] = GB1_q_a[7]_PORT_A_data_out_reg[0];


--GB1_q_a[6] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[6] at M4K_X33_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[6]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[6]_PORT_A_address_reg = DFFE(GB1_q_a[6]_PORT_A_address, GB1_q_a[6]_clock_0, , , );
GB1_q_a[6]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[6]_PORT_A_data_out = MEMORY(, , GB1_q_a[6]_PORT_A_address_reg, , , , , , GB1_q_a[6]_clock_0, , , , , );
GB1_q_a[6]_PORT_A_data_out_reg = DFFE(GB1_q_a[6]_PORT_A_data_out, GB1_q_a[6]_clock_0, , , );
GB1_q_a[6] = GB1_q_a[6]_PORT_A_data_out_reg[0];


--GB1_q_a[5] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[5] at M4K_X33_Y6
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[5]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[5]_PORT_A_address_reg = DFFE(GB1_q_a[5]_PORT_A_address, GB1_q_a[5]_clock_0, , , );
GB1_q_a[5]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[5]_PORT_A_data_out = MEMORY(, , GB1_q_a[5]_PORT_A_address_reg, , , , , , GB1_q_a[5]_clock_0, , , , , );
GB1_q_a[5]_PORT_A_data_out_reg = DFFE(GB1_q_a[5]_PORT_A_data_out, GB1_q_a[5]_clock_0, , , );
GB1_q_a[5] = GB1_q_a[5]_PORT_A_data_out_reg[0];


--GB1_q_a[4] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[4] at M4K_X33_Y9
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[4]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[4]_PORT_A_address_reg = DFFE(GB1_q_a[4]_PORT_A_address, GB1_q_a[4]_clock_0, , , );
GB1_q_a[4]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[4]_PORT_A_data_out = MEMORY(, , GB1_q_a[4]_PORT_A_address_reg, , , , , , GB1_q_a[4]_clock_0, , , , , );
GB1_q_a[4]_PORT_A_data_out_reg = DFFE(GB1_q_a[4]_PORT_A_data_out, GB1_q_a[4]_clock_0, , , );
GB1_q_a[4] = GB1_q_a[4]_PORT_A_data_out_reg[0];


--GB1_q_a[3] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[3] at M4K_X33_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[3]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[3]_PORT_A_address_reg = DFFE(GB1_q_a[3]_PORT_A_address, GB1_q_a[3]_clock_0, , , );
GB1_q_a[3]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[3]_PORT_A_data_out = MEMORY(, , GB1_q_a[3]_PORT_A_address_reg, , , , , , GB1_q_a[3]_clock_0, , , , , );
GB1_q_a[3]_PORT_A_data_out_reg = DFFE(GB1_q_a[3]_PORT_A_data_out, GB1_q_a[3]_clock_0, , , );
GB1_q_a[3] = GB1_q_a[3]_PORT_A_data_out_reg[0];


--GB1_q_a[2] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[2] at M4K_X33_Y7
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[2]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[2]_PORT_A_address_reg = DFFE(GB1_q_a[2]_PORT_A_address, GB1_q_a[2]_clock_0, , , );
GB1_q_a[2]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[2]_PORT_A_data_out = MEMORY(, , GB1_q_a[2]_PORT_A_address_reg, , , , , , GB1_q_a[2]_clock_0, , , , , );
GB1_q_a[2]_PORT_A_data_out_reg = DFFE(GB1_q_a[2]_PORT_A_data_out, GB1_q_a[2]_clock_0, , , );
GB1_q_a[2] = GB1_q_a[2]_PORT_A_data_out_reg[0];


--GB1_q_a[1] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[1] at M4K_X19_Y6
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[1]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , );
GB1_q_a[1]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[1]_PORT_A_data_out = MEMORY(, , GB1_q_a[1]_PORT_A_address_reg, , , , , , GB1_q_a[1]_clock_0, , , , , );
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, , , );
GB1_q_a[1] = GB1_q_a[1]_PORT_A_data_out_reg[0];


--GB1_q_a[0] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[0] at M4K_X19_Y7
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[0]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , );
GB1_q_a[0]_clock_0 = GLOBAL(DB01_87);
GB1_q_a[0]_PORT_A_data_out = MEMORY(, , GB1_q_a[0]_PORT_A_address_reg, , , , , , GB1_q_a[0]_clock_0, , , , , );
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, , , );
GB1_q_a[0] = GB1_q_a[0]_PORT_A_data_out_reg[0];


--DB9_9 is 48:inst4|74161:inst|f74161:sub|9 at LC_X45_Y13_N1
--operation mode is normal

DB9_9_lut_out = !DB9_9;
DB9_9 = DFFEAS(DB9_9_lut_out, GLOBAL(48mhz), VCC, , , , , , );


--DB9_110 is 48:inst4|74161:inst|f74161:sub|110 at LC_X8_Y13_N2
--operation mode is arithmetic

DB9_110_lut_out = DB9_110 $ (!DB9_95);
DB9_110 = DFFEAS(DB9_110_lut_out, GLOBAL(48mhz), VCC, , , , , !E1_inst2, );

--DB9_105 is 48:inst4|74161:inst|f74161:sub|105 at LC_X8_Y13_N2
--operation mode is arithmetic

DB9_105_cout_0 = DB9_110 & (!DB9_95);
DB9_105 = CARRY(DB9_105_cout_0);

--DB9L9 is 48:inst4|74161:inst|f74161:sub|105~COUT1_2 at LC_X8_Y13_N2
--operation mode is arithmetic

DB9L9_cout_1 = DB9_110 & (!DB9L6);
DB9L9 = CARRY(DB9L9_cout_1);


--E1L2 is 48:inst4|inst2~29 at LC_X8_Y13_N8
--operation mode is normal

E1L2 = DB01_87 & DB9_110;


--DB9_99 is 48:inst4|74161:inst|f74161:sub|99 at LC_X8_Y13_N1
--operation mode is arithmetic

DB9_99_lut_out = DB9_99 $ (DB9_85);
DB9_99 = DFFEAS(DB9_99_lut_out, GLOBAL(48mhz), VCC, , , , , !E1_inst2, );

--DB9_95 is 48:inst4|74161:inst|f74161:sub|95 at LC_X8_Y13_N1
--operation mode is arithmetic

DB9_95_cout_0 = !DB9_85 # !DB9_99;
DB9_95 = CARRY(DB9_95_cout_0);

--DB9L6 is 48:inst4|74161:inst|f74161:sub|95~COUT1 at LC_X8_Y13_N1
--operation mode is arithmetic

DB9L6_cout_1 = !DB9L3 # !DB9_99;
DB9L6 = CARRY(DB9L6_cout_1);


--DB9_87 is 48:inst4|74161:inst|f74161:sub|87 at LC_X8_Y13_N0
--operation mode is arithmetic

DB9_87_lut_out = DB9_9 $ DB9_87;
DB9_87 = DFFEAS(DB9_87_lut_out, GLOBAL(48mhz), VCC, , , , , !E1_inst2, );

--DB9_85 is 48:inst4|74161:inst|f74161:sub|85 at LC_X8_Y13_N0
--operation mode is arithmetic

DB9_85_cout_0 = DB9_9 & DB9_87;
DB9_85 = CARRY(DB9_85_cout_0);

--DB9L3 is 48:inst4|74161:inst|f74161:sub|85~COUT1_2 at LC_X8_Y13_N0
--operation mode is arithmetic

DB9L3_cout_1 = DB9_9 & DB9_87;
DB9L3 = CARRY(DB9L3_cout_1);


--E1_inst2 is 48:inst4|inst2 at LC_X8_Y13_N5
--operation mode is normal

E1_inst2 = !DB9_9 # !E1L2 # !DB9_87 # !DB9_99;


--DB8_87 is 1hz1khz:inst3|fenpin:inst3|74161:inst2|f74161:sub|87 at LC_X9_Y13_N9
--operation mode is normal

DB8_87_carry_eqn = (!DB7_81 & DB8_81) # (DB7_81 & DB8L3);
DB8_87_lut_out = DB8_87 $ (DB8_87_carry_eqn);
DB8_87 = DFFEAS(DB8_87_lut_out, GLOBAL(DB2_87), VCC, , , , , , );


--HB3_7 is cepin:inst9|74160:inst2|7 at LC_X43_Y12_N0
--operation mode is normal

HB3_7_lut_out = HB3_9 & J1_inst10 & (HB3_7) # !HB3_9 & (HB3L6 $ (J1_inst10 & HB3_7));
HB3_7 = DFFEAS(HB3_7_lut_out, GLOBAL(GB1_q_a[9]), cl, , , , , , );


--inst13 is inst13 at LC_X42_Y15_N2
--operation mode is normal

inst13_lut_out = !inst13;
inst13 = DFFEAS(inst13_lut_out, DB5_87, VCC, , , , , , );


--HB2_7 is cepin:inst9|74160:inst1|7 at LC_X42_Y13_N9
--operation mode is normal

HB2_7_lut_out = HB2_7 & (J1_inst10 $ (HB2L6 & !HB2_9)) # !HB2_7 & (HB2L6 & !HB2_9);
HB2_7 = DFFEAS(HB2_7_lut_out, GLOBAL(GB1_q_a[9]), cl, , , , , , );


--HB1_7 is cepin:inst9|74160:inst|7 at LC_X42_Y15_N5
--operation mode is normal

HB1_7_lut_out = J1_inst10 & (HB1_7 $ (!HB1_9 & HB1L6)) # !J1_inst10 & (!HB1_9 & HB1L6);
HB1_7 = DFFEAS(HB1_7_lut_out, GLOBAL(GB1_q_a[9]), cl, , , , , , );


--HB4_7 is cepin:inst9|74160:inst3|7 at LC_X43_Y12_N1
--operation mode is normal

HB4_7_lut_out = HB4_9 & J1_inst10 & HB4_7 # !HB4_9 & (HB4L6 $ (J1_inst10 & HB4_7));
HB4_7 = DFFEAS(HB4_7_lut_out, GLOBAL(GB1_q_a[9]), cl, , , , , , );


--DB31L6 is kuopx161:inst16|74161:inst|f74161:sub|82~0 at LC_X29_Y10_N0
--operation mode is arithmetic

DB31L6 = DB01_87 & key1;

--DB31_82 is kuopx161:inst16|74161:inst|f74161:sub|82 at LC_X29_Y10_N0
--operation mode is arithmetic

DB31_82_cout_0 = DB01_87 & key1;
DB31_82 = CARRY(DB31_82_cout_0);

--DB31L7 is kuopx161:inst16|74161:inst|f74161:sub|82~COUT1_2 at LC_X29_Y10_N0
--operation mode is arithmetic

DB31L7_cout_1 = DB01_87 & key1;
DB31L7 = CARRY(DB31L7_cout_1);


--HB11L6 is kuopx:inst19|74160:inst4|47~55 at LC_X40_Y8_N6
--operation mode is normal

HB11L6 = DB31L6 & HB9_6 & HB01_6 & HB9_9;


--K2L2 is kuopx:inst19|inst5~30 at LC_X39_Y8_N1
--operation mode is normal

K2L2 = HB01_6 & HB11_7 & HB9_6 & HB01_8;


--K2_inst5 is kuopx:inst19|inst5 at LC_X39_Y8_N5
--operation mode is normal

K2_inst5 = HB9_8 & (K2L2);


--HB11L01 is kuopx:inst19|74160:inst4|50~24 at LC_X41_Y8_N8
--operation mode is normal

HB11L01 = HB11_6 & !K2_inst5 & HB11L6 & HB01_9;


--HB11L7 is kuopx:inst19|74160:inst4|47~56 at LC_X40_Y8_N8
--operation mode is normal

HB11L7 = DB31L6 & HB9_6 & (HB9_9);


--HB01L6 is kuopx:inst19|74160:inst1|50~24 at LC_X40_Y8_N1
--operation mode is normal

HB01L6 = HB01_6 & HB11L7 & (!K2L2 # !HB9_8);


--HB8L6 is kuopx:inst14|74160:inst4|47~55 at LC_X41_Y6_N8
--operation mode is normal

HB8L6 = HB7_6 & HB6_6 & DB31L6 & HB6_9;


--K1L2 is kuopx:inst14|inst5~30 at LC_X42_Y6_N1
--operation mode is normal

K1L2 = HB7_6 & HB6_6 & HB7_8 & HB8_7;


--K1_inst5 is kuopx:inst14|inst5 at LC_X42_Y6_N7
--operation mode is normal

K1_inst5 = HB6_8 & (K1L2);


--HB8L01 is kuopx:inst14|74160:inst4|50~24 at LC_X42_Y8_N2
--operation mode is normal

HB8L01 = !K1_inst5 & HB8_6 & HB7_9 & HB8L6;


--HB8L7 is kuopx:inst14|74160:inst4|47~56 at LC_X41_Y6_N2
--operation mode is normal

HB8L7 = HB6_6 & DB31L6 & HB6_9;


--HB7L6 is kuopx:inst14|74160:inst1|50~24 at LC_X41_Y6_N4
--operation mode is normal

HB7L6 = HB7_6 & HB8L7 & (!K1L2 # !HB6_8);


--HB6L6 is kuopx:inst14|74160:inst|50~26 at LC_X41_Y6_N6
--operation mode is normal

HB6L6 = HB6_6 & DB31L6 & (!K1L2 # !HB6_8);


--HB9L6 is kuopx:inst19|74160:inst|50~26 at LC_X40_Y8_N5
--operation mode is normal

HB9L6 = HB9_6 & DB31L6 & (!HB9_8 # !K2L2);


--HB5_7 is cepin:inst9|74160:inst4|7 at LC_X43_Y13_N7