dds_top.fit.eqn

实现数字频率合成。能产生任意频率的正弦信号、方波信号、梯形波等

HB6_8_lut_out = K1L2 & HB6_7 & (HB6L6) # !K1L2 & (HB6_8 $ (HB6_7 & HB6L6));
HB6_8 = DFFEAS(HB6_8_lut_out, GLOBAL(cpx0), cl, , , , , , );


--R1L51 is 74157:inst22|24~63 at LC_X42_Y8_N0
--operation mode is normal

R1L51 = HB21_6 & (HB21_7) # !HB21_6 & (HB21_7 & (HB8_8) # !HB21_7 & HB6_8);


--HB9_8 is kuopx:inst19|74160:inst|8 at LC_X40_Y8_N4
--operation mode is normal

HB9_8_lut_out = K2L2 & HB9_7 & (HB9L6) # !K2L2 & (HB9_8 $ (HB9_7 & HB9L6));
HB9_8 = DFFEAS(HB9_8_lut_out, GLOBAL(cpp0), cl, , , , , , );


--R1L61 is 74157:inst22|24~64 at LC_X42_Y8_N7
--operation mode is normal

R1L61 = R1L51 & (HB9_8 # !HB21_6) # !R1L51 & HB7_8 & HB21_6;


--R1L71 is 74157:inst22|24~65 at LC_X42_Y8_N5
--operation mode is normal

R1L71 = HB21_8 & (KB7L1 # key7) # !HB21_8 & R1L61 & (!key7);


--KB3L1 is cepin:inst9|24x4:inst13|74151:inst2|f74151:sub|73~14 at LC_X42_Y13_N4
--operation mode is normal

AB21_14_qfbk = AB21_14;
KB3L1 = !HB21_7 & (AB21_14_qfbk # HB21_6);

--AB21_14 is cepin:inst9|74175:inst9|14 at LC_X42_Y13_N4
--operation mode is normal

AB21_14 = DFFEAS(KB3L1, !GLOBAL(inst13), cl, , , HB5_8, , , VCC);


--R1L81 is 74157:inst22|24~66 at LC_X42_Y8_N6
--operation mode is normal

R1L81 = key7 & (R1L71 & (KB3L1) # !R1L71 & R1L41) # !key7 & (R1L71);


--AB8_16 is cepin:inst9|74175:inst5|16 at LC_X41_Y11_N3
--operation mode is normal

AB8_16_lut_out = HB1_6;
AB8_16 = DFFEAS(AB8_16_lut_out, !GLOBAL(inst13), cl, , , , , , );


--R1L1 is 74157:inst22|22~40 at LC_X41_Y11_N8
--operation mode is normal

AB9_16_qfbk = AB9_16;
R1L1 = HB21_6 & (HB21_7 # AB9_16_qfbk) # !HB21_6 & !HB21_7 & (AB8_16);

--AB9_16 is cepin:inst9|74175:inst6|16 at LC_X41_Y11_N8
--operation mode is normal

AB9_16 = DFFEAS(R1L1, !GLOBAL(inst13), cl, , , HB2_6, , , VCC);


--AB11_16 is cepin:inst9|74175:inst8|16 at LC_X42_Y12_N5
--operation mode is normal

AB11_16_lut_out = GND;
AB11_16 = DFFEAS(AB11_16_lut_out, !GLOBAL(inst13), cl, , , HB4_6, , , VCC);


--R1L2 is 74157:inst22|22~41 at LC_X42_Y13_N6
--operation mode is normal

AB01_16_qfbk = AB01_16;
R1L2 = HB21_7 & (R1L1 & (AB11_16) # !R1L1 & AB01_16_qfbk) # !HB21_7 & R1L1;

--AB01_16 is cepin:inst9|74175:inst7|16 at LC_X42_Y13_N6
--operation mode is normal

AB01_16 = DFFEAS(R1L2, !GLOBAL(inst13), cl, , , HB3_6, , , VCC);


--HB11_6 is kuopx:inst19|74160:inst4|6 at LC_X41_Y8_N7
--operation mode is normal

HB11_6_lut_out = !K2_inst5 & (HB11_6 $ (HB11L6 & HB01_9));
HB11_6 = DFFEAS(HB11_6_lut_out, GLOBAL(cpp0), cl, , , , , , );


--HB01_6 is kuopx:inst19|74160:inst1|6 at LC_X39_Y8_N7
--operation mode is normal

HB01_6_lut_out = K2L2 & !HB9_8 & (HB01_6 $ HB11L7) # !K2L2 & (HB01_6 $ HB11L7);
HB01_6 = DFFEAS(HB01_6_lut_out, GLOBAL(cpp0), cl, , , , , , );


--KB5L1 is 24x4:inst18|74151:inst|f74151:sub|73~56 at LC_X41_Y11_N7
--operation mode is normal

KB5L1 = !HB21_7 & (HB21_6 & (HB11_6) # !HB21_6 & HB01_6);


--HB7_6 is kuopx:inst14|74160:inst1|6 at LC_X42_Y6_N6
--operation mode is normal

HB7_6_lut_out = K1L2 & !HB6_8 & (HB7_6 $ HB8L7) # !K1L2 & (HB7_6 $ HB8L7);
HB7_6 = DFFEAS(HB7_6_lut_out, GLOBAL(cpx0), cl, , , , , , );


--HB8_6 is kuopx:inst14|74160:inst4|6 at LC_X42_Y8_N8
--operation mode is normal

HB8_6_lut_out = !K1_inst5 & (HB8_6 $ (HB7_9 & HB8L6));
HB8_6 = DFFEAS(HB8_6_lut_out, GLOBAL(cpx0), cl, , , , , , );


--HB6_6 is kuopx:inst14|74160:inst|6 at LC_X42_Y6_N0
--operation mode is normal

HB6_6_lut_out = K1L2 & !HB6_8 & (HB6_6 $ DB31L6) # !K1L2 & (HB6_6 $ DB31L6);
HB6_6 = DFFEAS(HB6_6_lut_out, GLOBAL(cpx0), cl, , , , , , );


--R1L3 is 74157:inst22|22~42 at LC_X42_Y8_N9
--operation mode is normal

R1L3 = HB21_6 & (HB21_7) # !HB21_6 & (HB21_7 & (HB8_6) # !HB21_7 & HB6_6);


--HB9_6 is kuopx:inst19|74160:inst|6 at LC_X39_Y8_N9
--operation mode is normal

HB9_6_lut_out = K2L2 & !HB9_8 & (HB9_6 $ DB31L6) # !K2L2 & (HB9_6 $ DB31L6);
HB9_6 = DFFEAS(HB9_6_lut_out, GLOBAL(cpp0), cl, , , , , , );


--R1L4 is 74157:inst22|22~43 at LC_X41_Y11_N5
--operation mode is normal

R1L4 = R1L3 & (HB9_6 # !HB21_6) # !R1L3 & HB7_6 & HB21_6;


--R1L5 is 74157:inst22|22~44 at LC_X41_Y11_N2
--operation mode is normal

R1L5 = HB21_8 & (key7 # KB5L1) # !HB21_8 & !key7 & (R1L4);


--KB1L1 is cepin:inst9|24x4:inst13|74151:inst|f74151:sub|73~14 at LC_X41_Y11_N0
--operation mode is normal

AB21_16_qfbk = AB21_16;
KB1L1 = !HB21_7 & (HB21_6 # AB21_16_qfbk);

--AB21_16 is cepin:inst9|74175:inst9|16 at LC_X41_Y11_N0
--operation mode is normal

AB21_16 = DFFEAS(KB1L1, !GLOBAL(inst13), cl, , , HB5_6, , , VCC);


--R1L6 is 74157:inst22|22~45 at LC_X41_Y11_N1
--operation mode is normal

R1L6 = R1L5 & (KB1L1 # !key7) # !R1L5 & (key7 & R1L2);


--EB1L1 is dtxs:inst5|7447:inst|81~7 at LC_X52_Y22_N4
--operation mode is normal

EB1L1 = R1L21 & (R1L42 # R1L81 & !R1L6) # !R1L21 & (R1L81 & !R1L6 # !R1L81 & R1L6 & !R1L42);


--EB1L2 is dtxs:inst5|7447:inst|82~42 at LC_X52_Y22_N9
--operation mode is normal

EB1L2 = R1L21 & (R1L42 # R1L81 & !R1L6) # !R1L21 & R1L81 & R1L6;


--EB1_83 is dtxs:inst5|7447:inst|83 at LC_X52_Y22_N8
--operation mode is normal

EB1_83 = R1L81 & (R1L42) # !R1L81 & R1L21 & !R1L6;


--EB1L4 is dtxs:inst5|7447:inst|84~51 at LC_X52_Y22_N7
--operation mode is normal

EB1L4 = R1L81 & (R1L6 $ !R1L21) # !R1L81 & R1L6 & !R1L21;


--EB1_85 is dtxs:inst5|7447:inst|85 at LC_X52_Y22_N5
--operation mode is normal

EB1_85 = R1L6 # R1L81 & !R1L21;


--EB1L6 is dtxs:inst5|7447:inst|86~41 at LC_X52_Y22_N2
--operation mode is normal

EB1L6 = R1L21 & (R1L6 # !R1L81) # !R1L21 & !R1L81 & R1L6 & !R1L42;


--EB1_87 is dtxs:inst5|7447:inst|87 at LC_X52_Y22_N6
--operation mode is normal

EB1_87 = R1L21 & R1L81 & R1L6 # !R1L21 & !R1L81 & (!R1L42);


--LB1_q_a[9] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[9] at M4K_X33_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[9]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[9]_PORT_A_address_reg = DFFE(LB1_q_a[9]_PORT_A_address, LB1_q_a[9]_clock_0, , , );
LB1_q_a[9]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[9]_PORT_A_data_out = MEMORY(, , LB1_q_a[9]_PORT_A_address_reg, , , , , , LB1_q_a[9]_clock_0, , , , , );
LB1_q_a[9]_PORT_A_data_out_reg = DFFE(LB1_q_a[9]_PORT_A_data_out, LB1_q_a[9]_clock_0, , , );
LB1_q_a[9] = LB1_q_a[9]_PORT_A_data_out_reg[0];


--Y1_inst11 is 9or:inst42|inst11 at LC_X27_Y10_N8
--operation mode is normal

AB81_15_qfbk = AB81_15;
Y1_inst11 = AB81_15_qfbk # LB1_q_a[9];

--AB81_15 is 10jcq_zong:inst41|74175:inst2|15 at LC_X27_Y10_N8
--operation mode is normal

AB81_15 = DFFEAS(Y1_inst11, A1L12, cl, , , AB3_15, , , VCC);


--LB1_q_a[8] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[8] at M4K_X33_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[8]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[8]_PORT_A_address_reg = DFFE(LB1_q_a[8]_PORT_A_address, LB1_q_a[8]_clock_0, , , );
LB1_q_a[8]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[8]_PORT_A_data_out = MEMORY(, , LB1_q_a[8]_PORT_A_address_reg, , , , , , LB1_q_a[8]_clock_0, , , , , );
LB1_q_a[8]_PORT_A_data_out_reg = DFFE(LB1_q_a[8]_PORT_A_data_out, LB1_q_a[8]_clock_0, , , );
LB1_q_a[8] = LB1_q_a[8]_PORT_A_data_out_reg[0];


--Y1_inst10 is 9or:inst42|inst10 at LC_X27_Y10_N2
--operation mode is normal

AB81_16_qfbk = AB81_16;
Y1_inst10 = LB1_q_a[8] # AB81_16_qfbk;

--AB81_16 is 10jcq_zong:inst41|74175:inst2|16 at LC_X27_Y10_N2
--operation mode is normal

AB81_16 = DFFEAS(Y1_inst10, A1L12, cl, , , AB3_16, , , VCC);


--LB1_q_a[7] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[7] at M4K_X33_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[7]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[7]_PORT_A_address_reg = DFFE(LB1_q_a[7]_PORT_A_address, LB1_q_a[7]_clock_0, , , );
LB1_q_a[7]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[7]_PORT_A_data_out = MEMORY(, , LB1_q_a[7]_PORT_A_address_reg, , , , , , LB1_q_a[7]_clock_0, , , , , );
LB1_q_a[7]_PORT_A_data_out_reg = DFFE(LB1_q_a[7]_PORT_A_data_out, LB1_q_a[7]_clock_0, , , );
LB1_q_a[7] = LB1_q_a[7]_PORT_A_data_out_reg[0];


--Y1_inst9 is 9or:inst42|inst9 at LC_X27_Y10_N4
--operation mode is normal

AB71_13_qfbk = AB71_13;
Y1_inst9 = AB71_13_qfbk # LB1_q_a[7];

--AB71_13 is 10jcq_zong:inst41|74175:inst1|13 at LC_X27_Y10_N4
--operation mode is normal

AB71_13 = DFFEAS(Y1_inst9, A1L12, cl, , , AB2_13, , , VCC);


--LB1_q_a[6] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[6] at M4K_X33_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[6]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[6]_PORT_A_address_reg = DFFE(LB1_q_a[6]_PORT_A_address, LB1_q_a[6]_clock_0, , , );
LB1_q_a[6]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[6]_PORT_A_data_out = MEMORY(, , LB1_q_a[6]_PORT_A_address_reg, , , , , , LB1_q_a[6]_clock_0, , , , , );
LB1_q_a[6]_PORT_A_data_out_reg = DFFE(LB1_q_a[6]_PORT_A_data_out, LB1_q_a[6]_clock_0, , , );
LB1_q_a[6] = LB1_q_a[6]_PORT_A_data_out_reg[0];


--Y1_inst8 is 9or:inst42|inst8 at LC_X27_Y10_N9
--operation mode is normal

AB71_14_qfbk = AB71_14;
Y1_inst8 = AB71_14_qfbk # LB1_q_a[6];

--AB71_14 is 10jcq_zong:inst41|74175:inst1|14 at LC_X27_Y10_N9
--operation mode is normal

AB71_14 = DFFEAS(Y1_inst8, A1L12, cl, , , AB2_14, , , VCC);


--LB1_q_a[5] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[5] at M4K_X19_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[5]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[5]_PORT_A_address_reg = DFFE(LB1_q_a[5]_PORT_A_address, LB1_q_a[5]_clock_0, , , );
LB1_q_a[5]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[5]_PORT_A_data_out = MEMORY(, , LB1_q_a[5]_PORT_A_address_reg, , , , , , LB1_q_a[5]_clock_0, , , , , );
LB1_q_a[5]_PORT_A_data_out_reg = DFFE(LB1_q_a[5]_PORT_A_data_out, LB1_q_a[5]_clock_0, , , );
LB1_q_a[5] = LB1_q_a[5]_PORT_A_data_out_reg[0];


--Y1_inst7 is 9or:inst42|inst7 at LC_X27_Y10_N3
--operation mode is normal

AB71_15_qfbk = AB71_15;
Y1_inst7 = LB1_q_a[5] # AB71_15_qfbk;

--AB71_15 is 10jcq_zong:inst41|74175:inst1|15 at LC_X27_Y10_N3
--operation mode is normal

AB71_15 = DFFEAS(Y1_inst7, A1L12, cl, , , AB2_15, , , VCC);


--LB1_q_a[4] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[4] at M4K_X33_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[4]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[4]_PORT_A_address_reg = DFFE(LB1_q_a[4]_PORT_A_address, LB1_q_a[4]_clock_0, , , );
LB1_q_a[4]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[4]_PORT_A_data_out = MEMORY(, , LB1_q_a[4]_PORT_A_address_reg, , , , , , LB1_q_a[4]_clock_0, , , , , );
LB1_q_a[4]_PORT_A_data_out_reg = DFFE(LB1_q_a[4]_PORT_A_data_out, LB1_q_a[4]_clock_0, , , );
LB1_q_a[4] = LB1_q_a[4]_PORT_A_data_out_reg[0];


--Y1_inst6 is 9or:inst42|inst6 at LC_X27_Y10_N5
--operation mode is normal

AB71_16_qfbk = AB71_16;
Y1_inst6 = AB71_16_qfbk # LB1_q_a[4];

--AB71_16 is 10jcq_zong:inst41|74175:inst1|16 at LC_X27_Y10_N5
--operation mode is normal

AB71_16 = DFFEAS(Y1_inst6, A1L12, cl, , , AB2_16, , , VCC);


--LB1_q_a[3] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[3] at M4K_X19_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[3]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[3]_PORT_A_address_reg = DFFE(LB1_q_a[3]_PORT_A_address, LB1_q_a[3]_clock_0, , , );
LB1_q_a[3]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[3]_PORT_A_data_out = MEMORY(, , LB1_q_a[3]_PORT_A_address_reg, , , , , , LB1_q_a[3]_clock_0, , , , , );
LB1_q_a[3]_PORT_A_data_out_reg = DFFE(LB1_q_a[3]_PORT_A_data_out, LB1_q_a[3]_clock_0, , , );
LB1_q_a[3] = LB1_q_a[3]_PORT_A_data_out_reg[0];


--Y1_inst5 is 9or:inst42|inst5 at LC_X26_Y10_N6
--operation mode is normal

AB61_13_qfbk = AB61_13;
Y1_inst5 = AB61_13_qfbk # LB1_q_a[3];

--AB61_13 is 10jcq_zong:inst41|74175:inst|13 at LC_X26_Y10_N6
--operation mode is normal

AB61_13 = DFFEAS(Y1_inst5, A1L12, cl, , , AB1_13, , , VCC);


--LB1_q_a[2] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[2] at M4K_X19_Y16
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[2]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[2]_PORT_A_address_reg = DFFE(LB1_q_a[2]_PORT_A_address, LB1_q_a[2]_clock_0, , , );
LB1_q_a[2]_clock_0 = GLOBAL(DB01_87);
LB1_q_a[2]_PORT_A_data_out = MEMORY(, , LB1_q_a[2]_PORT_A_address_reg, , , , , , LB1_q_a[2]_clock_0, , , , , );
LB1_q_a[2]_PORT_A_data_out_reg = DFFE(LB1_q_a[2]_PORT_A_data_out, LB1_q_a[2]_clock_0, , , );
LB1_q_a[2] = LB1_q_a[2]_PORT_A_data_out_reg[0];


--Y1_inst4 is 9or:inst42|inst4 at LC_X27_Y10_N0
--operation mode is normal

AB61_14_qfbk = AB61_14;
Y1_inst4 = AB61_14_qfbk # LB1_q_a[2];

--AB61_14 is 10jcq_zong:inst41|74175:inst|14 at LC_X27_Y10_N0