tennis.tan.qmsg

里面是个乒乓游戏机的试验程序 要的就下载吧 挺好的 用FPGA

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "board:ubda\|serclk ballctrl:ucpu\|serve bain 100 ps " "Info: Found hold time violation between source  pin or register \"board:ubda\|serclk\" and destination pin or register \"ballctrl:ucpu\|serve\" for clock \"bain\" (Hold time is 100 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.300 ns + Largest " "Info: + Largest clock skew is 4.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bain destination 6.700 ns + Longest register " "Info: + Longest clock path from clock \"bain\" to destination register is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns bain 1 CLK PIN_125 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 6; CLK Node = 'bain'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bain } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 3.900 ns ballctrl:ucpu\|bdout 2 COMB LC3_B18 1 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 3.900 ns; Loc. = LC3_B18; Fanout = 1; COMB Node = 'ballctrl:ucpu\|bdout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { bain ballctrl:ucpu|bdout } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 6.700 ns ballctrl:ucpu\|serve 3 REG LC8_B22 4 " "Info: 3: + IC(1.200 ns) + CELL(1.600 ns) = 6.700 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu\|serve'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 77.61 % ) " "Info: Total cell delay = 5.200 ns ( 77.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 22.39 % ) " "Info: Total interconnect delay = 1.500 ns ( 22.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { bain ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.700 ns" { bain bain~out ballctrl:ucpu|bdout ballctrl:ucpu|serve } { 0.000ns 0.000ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.600ns 1.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bain source 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"bain\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns bain 1 CLK PIN_125 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 6; CLK Node = 'bain'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bain } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns board:ubda\|serclk 2 REG LC3_B22 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_B22; Fanout = 3; REG Node = 'board:ubda\|serclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { bain board:ubda|serclk } "NODE_NAME" } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { bain board:ubda|serclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { bain bain~out board:ubda|serclk } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { bain ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.700 ns" { bain bain~out ballctrl:ucpu|bdout ballctrl:ucpu|serve } { 0.000ns 0.000ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.600ns 1.600ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { bain board:ubda|serclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { bain bain~out board:ubda|serclk } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns - " "Info: - Micro clock to output delay of source is 0.500 ns" {  } { { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns - Shortest register register " "Info: - Shortest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns board:ubda\|serclk 1 REG LC3_B22 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B22; Fanout = 3; REG Node = 'board:ubda\|serclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { board:ubda|serclk } "NODE_NAME" } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 1.700 ns ballctrl:ucpu\|serclk 2 COMB LC1_B22 2 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC1_B22; Fanout = 2; COMB Node = 'ballctrl:ucpu\|serclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { board:ubda|serclk ballctrl:ucpu|serclk } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 3.700 ns ballctrl:ucpu\|serve 3 REG LC8_B22 4 " "Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 3.700 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu\|serve'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { ballctrl:ucpu|serclk ballctrl:ucpu|serve } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 83.78 % ) " "Info: Total cell delay = 3.100 ns ( 83.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 16.22 % ) " "Info: Total interconnect delay = 0.600 ns ( 16.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { board:ubda|serclk ballctrl:ucpu|serclk ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.700 ns" { board:ubda|serclk ballctrl:ucpu|serclk ballctrl:ucpu|serve } { 0.000ns 0.300ns 0.300ns } { 0.000ns 1.400ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 12 -1 0 } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { bain ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.700 ns" { bain bain~out ballctrl:ucpu|bdout ballctrl:ucpu|serve } { 0.000ns 0.000ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.600ns 1.600ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { bain board:ubda|serclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { bain bain~out board:ubda|serclk } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { board:ubda|serclk ballctrl:ucpu|serclk ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.700 ns" { board:ubda|serclk ballctrl:ucpu|serclk ballctrl:ucpu|serve } { 0.000ns 0.300ns 0.300ns } { 0.000ns 1.400ns 1.700ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "bain countah\[1\] cou4:uah\|lpm_counter:qqout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 15.900 ns register " "Info: tco from clock \"bain\" to destination pin \"countah\[1\]\" through register \"cou4:uah\|lpm_counter:qqout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]\" is 15.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bain source 7.400 ns + Longest register " "Info: + Longest clock path from clock \"bain\" to source register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns bain 1 CLK PIN_125 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 6; CLK Node = 'bain'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bain } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns board:ubda\|couclk 2 REG LC2_B22 9 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC2_B22; Fanout = 9; REG Node = 'board:ubda\|couclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { bain board:ubda|couclk } "NODE_NAME" } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.500 ns) 5.100 ns cou10:ual\|cout 3 REG LC6_C20 7 " "Info: 3: + IC(1.700 ns) + CELL(0.500 ns) = 5.100 ns; Loc. = LC6_C20; Fanout = 7; REG Node = 'cou10:ual\|cout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { board:ubda|couclk cou10:ual|cout } "NODE_NAME" } } { "COU10.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU10.VHD" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.000 ns) 7.400 ns cou4:uah\|lpm_counter:qqout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 4 REG LC2_A3 5 " "Info: 4: + IC(2.300 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC2_A3; Fanout = 5; REG Node = 'cou4:uah\|lpm_counter:qqout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { cou10:ual|cout cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 40.54 % ) " "Info: Total cell delay = 3.000 ns ( 40.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.400 ns ( 59.46 % ) " "Info: Total interconnect delay = 4.400 ns ( 59.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.400 ns" { bain board:ubda|couclk cou10:ual|cout cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.400 ns" { bain bain~out board:ubda|couclk cou10:ual|cout cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 0.400ns 1.700ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register pin " "Info: + Longest register to pin delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cou4:uah\|lpm_counter:qqout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 1 REG LC2_A3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A3; Fanout = 5; REG Node = 'cou4:uah\|lpm_counter:qqout_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(6.300 ns) 8.000 ns countah\[1\] 2 PIN PIN_8 0 " "Info: 2: + IC(1.700 ns) + CELL(6.300 ns) = 8.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'countah\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] countah[1] } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 78.75 % ) " "Info: Total cell delay = 6.300 ns ( 78.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 21.25 % ) " "Info: Total interconnect delay = 1.700 ns ( 21.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] countah[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.000 ns" { cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] countah[1] } { 0.000ns 1.700ns } { 0.000ns 6.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.400 ns" { bain board:ubda|couclk cou10:ual|cout cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.400 ns" { bain bain~out board:ubda|couclk cou10:ual|cout cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 0.400ns 1.700ns 2.300ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] countah[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.000 ns" { cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] countah[1] } { 0.000ns 1.700ns } { 0.000ns 6.300ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "souclk speaker 11.300 ns Longest " "Info: Longest tpd from source pin \"souclk\" to destination pin \"speaker\" is 11.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns souclk 1 PIN PIN_56 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 1; PIN Node = 'souclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { souclk } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.700 ns) 3.800 ns sound:usound\|sout~34 2 COMB LC5_B23 1 " "Info: 2: + IC(0.100 ns) + CELL(1.700 ns) = 3.800 ns; Loc. = LC5_B23; Fanout = 1; COMB Node = 'sound:usound\|sout~34'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { souclk sound:usound|sout~34 } "NODE_NAME" } } { "SOUND.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/SOUND.VHD" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(6.300 ns) 11.300 ns speaker 3 PIN PIN_21 0 " "Info: 3: + IC(1.200 ns) + CELL(6.300 ns) = 11.300 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'speaker'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { sound:usound|sout~34 speaker } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 88.50 % ) " "Info: Total cell delay = 10.000 ns ( 88.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 11.50 % ) " "Info: Total interconnect delay = 1.300 ns ( 11.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.300 ns" { souclk sound:usound|sout~34 speaker } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.300 ns" { souclk souclk~out sound:usound|sout~34 speaker } { 0.000ns 0.000ns 0.100ns 1.200ns } { 0.000ns 2.000ns 1.700ns 6.300ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk ballout\[2\] ball:uball\|lamp\[3\] 10.100 ns register " "Info: Minimum tco from clock \"clk\" to destination pin \"ballout\[2\]\" through register \"ball:uball\|lamp\[3\]\" i