📄 tennis.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register ball:uball\|lamp\[3\] ball:uball\|lamp\[2\] 200.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 200.0 MHz between source register \"ball:uball\|lamp\[3\]\" and destination register \"ball:uball\|lamp\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.900 ns + Longest register register " "Info: + Longest register to register delay is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ball:uball\|lamp\[3\] 1 REG LC7_B24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_B24; Fanout = 3; REG Node = 'ball:uball\|lamp\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ball:uball|lamp[3] } "NODE_NAME" } } { "BALL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.000 ns) 1.900 ns ball:uball\|lamp\[2\] 2 REG LC2_B23 3 " "Info: 2: + IC(0.900 ns) + CELL(1.000 ns) = 1.900 ns; Loc. = LC2_B23; Fanout = 3; REG Node = 'ball:uball\|lamp\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ball:uball|lamp[3] ball:uball|lamp[2] } "NODE_NAME" } } { "BALL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.000 ns ( 52.63 % ) " "Info: Total cell delay = 1.000 ns ( 52.63 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 47.37 % ) " "Info: Total interconnect delay = 0.900 ns ( 47.37 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ball:uball|lamp[3] ball:uball|lamp[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { ball:uball|lamp[3] ball:uball|lamp[2] } { 0.000ns 0.900ns } { 0.000ns 1.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 11 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 11; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns ball:uball\|lamp\[2\] 2 REG LC2_B23 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_B23; Fanout = 3; REG Node = 'ball:uball\|lamp\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { clk ball:uball|lamp[2] } "NODE_NAME" } } { "BALL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { clk ball:uball|lamp[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { clk clk~out ball:uball|lamp[2] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 11 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 11; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns ball:uball\|lamp\[3\] 2 REG LC7_B24 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_B24; Fanout = 3; REG Node = 'ball:uball\|lamp\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { clk ball:uball|lamp[3] } "NODE_NAME" } } { "BALL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { clk ball:uball|lamp[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { clk clk~out ball:uball|lamp[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { clk ball:uball|lamp[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { clk clk~out ball:uball|lamp[2] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { clk ball:uball|lamp[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { clk clk~out ball:uball|lamp[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "BALL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "BALL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ball:uball|lamp[3] ball:uball|lamp[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { ball:uball|lamp[3] ball:uball|lamp[2] } { 0.000ns 0.900ns } { 0.000ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { clk ball:uball|lamp[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { clk clk~out ball:uball|lamp[2] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { clk ball:uball|lamp[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { clk clk~out ball:uball|lamp[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ball:uball|lamp[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { ball:uball|lamp[2] } { } { } } } { "BALL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 17 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "bain register ballctrl:ucpu\|serve register board:ubda\|couclk 63.29 MHz 15.8 ns Internal " "Info: Clock \"bain\" has Internal fmax of 63.29 MHz between source register \"ballctrl:ucpu\|serve\" and destination register \"board:ubda\|couclk\" (period= 15.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.000 ns + Longest register register " "Info: + Longest register to register delay is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ballctrl:ucpu\|serve 1 REG LC8_B22 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu\|serve'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ballctrl:ucpu|serve } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 1.700 ns board:ubda\|couclk~1 2 COMB LC6_B22 1 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC6_B22; Fanout = 1; COMB Node = 'board:ubda\|couclk~1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { ballctrl:ucpu|serve board:ubda|couclk~1 } "NODE_NAME" } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 3.000 ns board:ubda\|couclk 3 REG LC2_B22 9 " "Info: 3: + IC(0.300 ns) + CELL(1.000 ns) = 3.000 ns; Loc. = LC2_B22; Fanout = 9; REG Node = 'board:ubda\|couclk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { board:ubda|couclk~1 board:ubda|couclk } "NODE_NAME" } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 80.00 % ) " "Info: Total cell delay = 2.400 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 20.00 % ) " "Info: Total interconnect delay = 0.600 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { ballctrl:ucpu|serve board:ubda|couclk~1 board:ubda|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { ballctrl:ucpu|serve board:ubda|couclk~1 board:ubda|couclk } { 0.000ns 0.300ns 0.300ns } { 0.000ns 1.400ns 1.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.300 ns - Smallest " "Info: - Smallest clock skew is -4.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bain destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"bain\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns bain 1 CLK PIN_125 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 6; CLK Node = 'bain'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bain } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns board:ubda\|couclk 2 REG LC2_B22 9 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_B22; Fanout = 9; REG Node = 'board:ubda\|couclk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { bain board:ubda|couclk } "NODE_NAME" } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { bain board:ubda|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { bain bain~out board:ubda|couclk } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bain source 6.700 ns - Longest register " "Info: - Longest clock path from clock \"bain\" to source register is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns bain 1 CLK PIN_125 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 6; CLK Node = 'bain'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bain } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 3.900 ns ballctrl:ucpu\|bdout 2 COMB LC3_B18 1 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 3.900 ns; Loc. = LC3_B18; Fanout = 1; COMB Node = 'ballctrl:ucpu\|bdout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { bain ballctrl:ucpu|bdout } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 6.700 ns ballctrl:ucpu\|serve 3 REG LC8_B22 4 " "Info: 3: + IC(1.200 ns) + CELL(1.600 ns) = 6.700 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu\|serve'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 77.61 % ) " "Info: Total cell delay = 5.200 ns ( 77.61 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 22.39 % ) " "Info: Total interconnect delay = 1.500 ns ( 22.39 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { bain ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.700 ns" { bain bain~out ballctrl:ucpu|bdout ballctrl:ucpu|serve } { 0.000ns 0.000ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.600ns 1.600ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { bain board:ubda|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { bain bain~out board:ubda|couclk } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { bain ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.700 ns" { bain bain~out ballctrl:ucpu|bdout ballctrl:ucpu|serve } { 0.000ns 0.000ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.600ns 1.600ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { ballctrl:ucpu|serve board:ubda|couclk~1 board:ubda|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { ballctrl:ucpu|serve board:ubda|couclk~1 board:ubda|couclk } { 0.000ns 0.300ns 0.300ns } { 0.000ns 1.400ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { bain board:ubda|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { bain bain~out board:ubda|couclk } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { bain ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.700 ns" { bain bain~out ballctrl:ucpu|bdout ballctrl:ucpu|serve } { 0.000ns 0.000ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.600ns 1.600ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "bbin register ballctrl:ucpu\|serve register board:ubdb\|couclk 64.94 MHz 15.4 ns Internal " "Info: Clock \"bbin\" has Internal fmax of 64.94 MHz between source register \"ballctrl:ucpu\|serve\" and destination register \"board:ubdb\|couclk\" (period= 15.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.000 ns + Longest register register " "Info: + Longest register to register delay is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ballctrl:ucpu\|serve 1 REG LC8_B22 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu\|serve'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ballctrl:ucpu|serve } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 1.700 ns board:ubdb\|couclk~1 2 COMB LC7_B22 1 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC7_B22; Fanout = 1; COMB Node = 'board:ubdb\|couclk~1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { ballctrl:ucpu|serve board:ubdb|couclk~1 } "NODE_NAME" } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 3.000 ns board:ubdb\|couclk 3 REG LC4_B22 9 " "Info: 3: + IC(0.300 ns) + CELL(1.000 ns) = 3.000 ns; Loc. = LC4_B22; Fanout = 9; REG Node = 'board:ubdb\|couclk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { board:ubdb|couclk~1 board:ubdb|couclk } "NODE_NAME" } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 80.00 % ) " "Info: Total cell delay = 2.400 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 20.00 % ) " "Info: Total interconnect delay = 0.600 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { ballctrl:ucpu|serve board:ubdb|couclk~1 board:ubdb|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { ballctrl:ucpu|serve board:ubdb|couclk~1 board:ubdb|couclk } { 0.000ns 0.300ns 0.300ns } { 0.000ns 1.400ns 1.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.100 ns - Smallest " "Info: - Smallest clock skew is -4.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bbin destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"bbin\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns bbin 1 CLK PIN_124 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 6; CLK Node = 'bbin'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bbin } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns board:ubdb\|couclk 2 REG LC4_B22 9 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_B22; Fanout = 9; REG Node = 'board:ubdb\|couclk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { bbin board:ubdb|couclk } "NODE_NAME" } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { bbin board:ubdb|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { bbin bbin~out board:ubdb|couclk } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bbin source 6.500 ns - Longest register " "Info: - Longest clock path from clock \"bbin\" to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns bbin 1 CLK PIN_124 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 6; CLK Node = 'bbin'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { bbin } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 3.700 ns ballctrl:ucpu\|bdout 2 COMB LC3_B18 1 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 3.700 ns; Loc. = LC3_B18; Fanout = 1; COMB Node = 'ballctrl:ucpu\|bdout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { bbin ballctrl:ucpu|bdout } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 6.500 ns ballctrl:ucpu\|serve 3 REG LC8_B22 4 " "Info: 3: + IC(1.200 ns) + CELL(1.600 ns) = 6.500 ns; Loc. = LC8_B22; Fanout = 4; REG Node = 'ballctrl:ucpu\|serve'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 76.92 % ) " "Info: Total cell delay = 5.000 ns ( 76.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 23.08 % ) " "Info: Total interconnect delay = 1.500 ns ( 23.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bbin ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { bbin bbin~out ballctrl:ucpu|bdout ballctrl:ucpu|serve } { 0.000ns 0.000ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.400ns 1.600ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { bbin board:ubdb|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { bbin bbin~out board:ubdb|couclk } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bbin ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { bbin bbin~out ballctrl:ucpu|bdout ballctrl:ucpu|serve } { 0.000ns 0.000ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.400ns 1.600ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } } { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { ballctrl:ucpu|serve board:ubdb|couclk~1 board:ubdb|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { ballctrl:ucpu|serve board:ubdb|couclk~1 board:ubdb|couclk } { 0.000ns 0.300ns 0.300ns } { 0.000ns 1.400ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { bbin board:ubdb|couclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { bbin bbin~out board:ubdb|couclk } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bbin ballctrl:ucpu|bdout ballctrl:ucpu|serve } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { bbin bbin~out ballctrl:ucpu|bdout ballctrl:ucpu|serve } { 0.000ns 0.000ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.400ns 1.600ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "bain 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"bain\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
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