tennis.tan.qmsg

里面是个乒乓游戏机的试验程序 要的就下载吧 挺好的 用FPGA

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "mway:uway\|way " "Warning: Node \"mway:uway\|way\" is a latch" {  } { { "MWAY.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/MWAY.VHD" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ballctrl:ucpu\|ballen " "Warning: Node \"ballctrl:ucpu\|ballen\" is a latch" {  } { { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 15 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ballctrl:ucpu\|serve " "Warning: Node \"ballctrl:ucpu\|serve\" is a latch" {  } { { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "bain " "Info: Assuming node \"bain\" is an undefined clock" {  } { { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "bain" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "bbin " "Info: Assuming node \"bbin\" is an undefined clock" {  } { { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "bbin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "clr " "Info: Assuming node \"clr\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "TENNIS.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 4 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "ballctrl:ucpu\|bdout " "Info: Detected gated clock \"ballctrl:ucpu\|bdout\" as buffer" {  } { { "BALLCTRL.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ballctrl:ucpu\|bdout" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "board:ubdb\|couclk " "Info: Detected ripple clock \"board:ubdb\|couclk\" as buffer" {  } { { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "board:ubdb\|couclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cou10:ubl\|cout " "Info: Detected ripple clock \"cou10:ubl\|cout\" as buffer" {  } { { "COU10.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU10.VHD" 10 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cou10:ubl\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "board:ubda\|couclk " "Info: Detected ripple clock \"board:ubda\|couclk\" as buffer" {  } { { "BOARD.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "board:ubda\|couclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cou10:ual\|cout " "Info: Detected ripple clock \"cou10:ual\|cout\" as buffer" {  } { { "COU10.VHD" "" { Text "G:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU10.VHD" 10 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cou10:ual\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ballctrl:ucpu\|comb~0 " "Info: Detected gated clock \"ballctrl:ucpu\|comb~0\" as buffer" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ballctrl:ucpu\|comb~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}