tennis.map.qmsg

里面是个乒乓游戏机的试验程序 要的就下载吧 挺好的 用FPGA

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ser BALLCTRL.VHD(33) " "Warning (10492): VHDL Process Statement warning at BALLCTRL.VHD(33): signal \"ser\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "BALLCTRL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "serve BALLCTRL.VHD(25) " "Warning (10631): VHDL Process Statement warning at BALLCTRL.VHD(25): inferring latch(es) for signal or variable \"serve\", which holds its previous value in one or more paths through the process" {  } { { "BALLCTRL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 25 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ballen BALLCTRL.VHD(25) " "Warning (10631): VHDL Process Statement warning at BALLCTRL.VHD(25): inferring latch(es) for signal or variable \"ballen\", which holds its previous value in one or more paths through the process" {  } { { "BALLCTRL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 25 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "ballen BALLCTRL.VHD(25) " "Info (10041): Verilog HDL or VHDL info at BALLCTRL.VHD(25): inferred latch for \"ballen\"" {  } { { "BALLCTRL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 25 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "serve BALLCTRL.VHD(25) " "Info (10041): Verilog HDL or VHDL info at BALLCTRL.VHD(25): inferred latch for \"serve\"" {  } { { "BALLCTRL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 25 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mway mway:uway " "Info: Elaborating entity \"mway\" for hierarchy \"mway:uway\"" {  } { { "TENNIS.VHD" "uway" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 60 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "way MWAY.VHD(11) " "Warning (10631): VHDL Process Statement warning at MWAY.VHD(11): inferring latch(es) for signal or variable \"way\", which holds its previous value in one or more paths through the process" {  } { { "MWAY.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/MWAY.VHD" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "way MWAY.VHD(11) " "Info (10041): Verilog HDL or VHDL info at MWAY.VHD(11): inferred latch for \"way\"" {  } { { "MWAY.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/MWAY.VHD" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ball ball:uball " "Info: Elaborating entity \"ball\" for hierarchy \"ball:uball\"" {  } { { "TENNIS.VHD" "uball" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 61 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "lamp BALL.VHD(29) " "Warning (10492): VHDL Process Statement warning at BALL.VHD(29): signal \"lamp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "BALL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sound sound:usound " "Info: Elaborating entity \"sound\" for hierarchy \"sound:usound\"" {  } { { "TENNIS.VHD" "usound" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 62 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "4 " "Info: Inferred 4 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cou4:uah\|qqout\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cou4:uah\|qqout\[0\]~4\"" {  } { { "COU4.VHD" "qqout\[0\]~4" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU4.VHD" 19 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cou10:ual\|qqout\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cou10:ual\|qqout\[0\]~4\"" {  } { { "COU10.VHD" "qqout\[0\]~4" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU10.VHD" 18 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cou4:ubh\|qqout\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cou4:ubh\|qqout\[0\]~4\"" {  } { { "COU4.VHD" "qqout\[0\]~4" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU4.VHD" 19 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cou10:ubl\|qqout\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cou10:ubl\|qqout\[0\]~4\"" {  } { { "COU10.VHD" "qqout\[0\]~4" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU10.VHD" 18 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "cou4:uah\|lpm_counter:qqout_rtl_0 " "Info: Elaborated megafunction instantiation \"cou4:uah\|lpm_counter:qqout_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "cou4:uah\|lpm_counter:qqout_rtl_0\|alt_counter_f10ke:wysi_counter cou4:uah\|lpm_counter:qqout_rtl_0 " "Info: Elaborated megafunction instantiation \"cou4:uah\|lpm_counter:qqout_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"cou4:uah\|lpm_counter:qqout_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 417 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "cou4:uah\|lpm_counter:qqout_rtl_0 " "Info: Instantiated megafunction \"cou4:uah\|lpm_counter:qqout_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "BALL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 17 -1 0 } } { "BALL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 17 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "78 " "Info: Implemented 78 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "26 " "Info: Implemented 26 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "47 " "Info: Implemented 47 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 16 17:55:00 2002 " "Info: Processing ended: Sun Jun 16 17:55:00 2002" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}