tennis.map.qmsg

里面是个乒乓游戏机的试验程序 要的就下载吧 挺好的 用FPGA

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 16 17:54:57 2002 " "Info: Processing started: Sun Jun 16 17:54:57 2002" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off TENNIS -c TENNIS " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TENNIS -c TENNIS" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BALL.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file BALL.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ball-ful " "Info: Found design unit 1: ball-ful" {  } { { "BALL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ball " "Info: Found entity 1: ball" {  } { { "BALL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALL.VHD" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BALLCTRL.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file BALLCTRL.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ballctrl-ful " "Info: Found design unit 1: ballctrl-ful" {  } { { "BALLCTRL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ballctrl " "Info: Found entity 1: ballctrl" {  } { { "BALLCTRL.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BALLCTRL.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BOARD.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file BOARD.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 board-ful " "Info: Found design unit 1: board-ful" {  } { { "BOARD.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 board " "Info: Found entity 1: board" {  } { { "BOARD.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/BOARD.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "COU10.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file COU10.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cou10-ful " "Info: Found design unit 1: cou10-ful" {  } { { "COU10.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU10.VHD" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cou10 " "Info: Found entity 1: cou10" {  } { { "COU10.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU10.VHD" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "COU4.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file COU4.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cou4-ful " "Info: Found design unit 1: cou4-ful" {  } { { "COU4.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU4.VHD" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cou4 " "Info: Found entity 1: cou4" {  } { { "COU4.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU4.VHD" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MWAY.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file MWAY.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mway-ful " "Info: Found design unit 1: mway-ful" {  } { { "MWAY.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/MWAY.VHD" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mway " "Info: Found entity 1: mway" {  } { { "MWAY.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/MWAY.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SOUND.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file SOUND.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sound-ful " "Info: Found design unit 1: sound-ful" {  } { { "SOUND.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/SOUND.VHD" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sound " "Info: Found entity 1: sound" {  } { { "SOUND.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/SOUND.VHD" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TENNIS.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file TENNIS.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TENNIS-ful " "Info: Found design unit 1: TENNIS-ful" {  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 TENNIS " "Info: Found entity 1: TENNIS" {  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "TENNIS " "Info: Elaborating entity \"TENNIS\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cah TENNIS.VHD(48) " "Warning (10036): Verilog HDL or VHDL warning at TENNIS.VHD(48): object \"cah\" assigned a value but never read" {  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 48 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cbh TENNIS.VHD(48) " "Warning (10036): Verilog HDL or VHDL warning at TENNIS.VHD(48): object \"cbh\" assigned a value but never read" {  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 48 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "serclk TENNIS.VHD(49) " "Warning (10036): Verilog HDL or VHDL warning at TENNIS.VHD(49): object \"serclk\" assigned a value but never read" {  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 49 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cou4 cou4:uah " "Info: Elaborating entity \"cou4\" for hierarchy \"cou4:uah\"" {  } { { "TENNIS.VHD" "uah" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 53 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "qqout COU4.VHD(31) " "Warning (10492): VHDL Process Statement warning at COU4.VHD(31): signal \"qqout\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "COU4.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU4.VHD" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cou10 cou10:ual " "Info: Elaborating entity \"cou10\" for hierarchy \"cou10:ual\"" {  } { { "TENNIS.VHD" "ual" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "qqout COU10.VHD(30) " "Warning (10492): VHDL Process Statement warning at COU10.VHD(30): signal \"qqout\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "COU10.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/COU10.VHD" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "board board:ubda " "Info: Elaborating entity \"board\" for hierarchy \"board:ubda\"" {  } { { "TENNIS.VHD" "ubda" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 57 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ballctrl ballctrl:ucpu " "Info: Elaborating entity \"ballctrl\" for hierarchy \"ballctrl:ucpu\"" {  } { { "TENNIS.VHD" "ucpu" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 59 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}