tennis.fit.qmsg

里面是个乒乓游戏机的试验程序 要的就下载吧 挺好的 用FPGA

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 16 17:55:02 2002 " "Info: Processing started: Sun Jun 16 17:55:02 2002" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off TENNIS -c TENNIS " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off TENNIS -c TENNIS" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "TENNIS EP1K30TC144-3 " "Info: Selected device EP1K30TC144-3 for design \"TENNIS\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IF10KE_F10KE_WIRE_LUT_INSERTED" "0 " "Info: Inserted 0 logic cells in first fitting attempt" {  } {  } 0 0 "Inserted %1!d! logic cells in first fitting attempt" 0 0}
{ "Error" "EF10KE_BIN_TOO_MANY_IO_CELL" "HALF_ROW_E1 5 3 " "Error: Can't place 5 I/O pins in region \"HALF_ROW_E1\" because the specified region cannot contain more than 3 I/O pins" { { "Info" "IFIT_FIT_NUM_USER_ASGN_CELL" "5 " "Info: Design contains 5 user assigned cells" {  } {  } 0 0 "Design contains %1!d! user assigned cells" 0 0}  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 5 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ballout[6] } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 5 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ballout[7] } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 6 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countbh[0] } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 6 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countbl[2] } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 6 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countbl[3] } "NODE_NAME" } }  } 0 0 "Can't place %2!d! I/O pins in region \"%1!s!\" because the specified region cannot contain more than %3!d! I/O pins" 0 0}
{ "Error" "EFIT_FIT_CELL_MULTI_ASGN" "countbl\[3\] ballout\[7\] PIN_86 " "Error: Can't place both node \"countbl\[3\]\" and node \"ballout\[7\]\" in region \"PIN_86\"" {  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 6 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countbl[3] } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 5 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ballout[7] } "NODE_NAME" } }  } 0 0 "Can't place both node \"%1!s!\" and node \"%2!s!\" in region \"%3!s!\"" 0 0}
{ "Error" "EFIT_FIT_CELL_MULTI_ASGN" "countbl\[2\] ballout\[6\] PIN_83 " "Error: Can't place both node \"countbl\[2\]\" and node \"ballout\[6\]\" in region \"PIN_83\"" {  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 6 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countbl[2] } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 5 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ballout[6] } "NODE_NAME" } }  } 0 0 "Can't place both node \"%1!s!\" and node \"%2!s!\" in region \"%3!s!\"" 0 0}
{ "Error" "EFIT_FIT_CELL_MULTI_ASGN" "countbl\[1\] ballout\[5\] PIN_82 " "Error: Can't place both node \"countbl\[1\]\" and node \"ballout\[5\]\" in region \"PIN_82\"" {  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 6 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countbl[1] } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 5 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ballout[5] } "NODE_NAME" } }  } 0 0 "Can't place both node \"%1!s!\" and node \"%2!s!\" in region \"%3!s!\"" 0 0}
{ "Error" "EFIT_FIT_CELL_MULTI_ASGN" "countbl\[0\] ballout\[4\] PIN_81 " "Error: Can't place both node \"countbl\[0\]\" and node \"ballout\[4\]\" in region \"PIN_81\"" {  } { { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 6 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countbl[0] } "NODE_NAME" } } { "TENNIS.VHD" "" { Text "H:/ww/6硬件电路的设计与实现(有完整的VHDL代码)/EP1C3_10_2_TENNIS/TENNIS.VHD" 5 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ballout[4] } "NODE_NAME" } }  } 0 0 "Can't place both node \"%1!s!\" and node \"%2!s!\" in region \"%3!s!\"" 0 0}
{ "Error" "EF10KE_FIT_FAIL" "" "Error: Can't find fit" {  } {  } 0 0 "Can't find fit" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Fitter 6 s 0 s Quartus II " "Error: Quartus II Fitter was unsuccessful. 6 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sun Jun 16 17:55:03 2002 " "Error: Processing ended: Sun Jun 16 17:55:03 2002" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}