📄 tennis.tan.rpt
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; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; bain ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; bbin ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; clr ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[3] ; ball:uball|lamp[2] ; clk ; clk ; None ; None ; 1.900 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[2] ; ball:uball|lamp[3] ; clk ; clk ; None ; None ; 1.900 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[2] ; ball:uball|lamp[1] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[1] ; ball:uball|lamp[0] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[1] ; ball:uball|lamp[2] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[4] ; ball:uball|lamp[3] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[3] ; ball:uball|lamp[4] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[5] ; ball:uball|lamp[4] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[4] ; ball:uball|lamp[5] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[6] ; ball:uball|lamp[5] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[5] ; ball:uball|lamp[6] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[7] ; ball:uball|lamp[6] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[6] ; ball:uball|lamp[7] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[8] ; ball:uball|lamp[7] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[7] ; ball:uball|lamp[8] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[0] ; ball:uball|lamp[1] ; clk ; clk ; None ; None ; 1.100 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[9] ; ball:uball|lamp[8] ; clk ; clk ; None ; None ; 1.100 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; ball:uball|lamp[8] ; ball:uball|lamp[9] ; clk ; clk ; None ; None ; 1.100 ns ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'bain' ;
+-------+------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 63.29 MHz ( period = 15.800 ns ) ; ballctrl:ucpu|serve ; board:ubda|couclk ; bain ; bain ; None ; None ; 3.000 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; ballctrl:ucpu|serve ; board:ubda|serclk ; bain ; bain ; None ; None ; 1.100 ns ;
; N/A ; 100.00 MHz ( period = 10.000 ns ) ; board:ubda|serclk ; ballctrl:ucpu|ballen ; bain ; bain ; None ; None ; 4.200 ns ;
; N/A ; 147.06 MHz ( period = 6.800 ns ) ; board:ubda|serclk ; ballctrl:ucpu|serve ; bain ; bain ; None ; None ; 3.700 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; bain ; bain ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; bain ; bain ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; bain ; bain ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; bain ; bain ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; bain ; bain ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; bain ; bain ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; bain ; bain ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; bain ; bain ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; bain ; bain ; None ; None ; 3.200 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; bain ; bain ; None ; None ; 3.000 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; bain ; bain ; None ; None ; 3.000 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; bain ; bain ; None ; None ; 3.000 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; bain ; bain ; None ; None ; 3.000 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; bain ; bain ; None ; None ; 3.000 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; bain ; bain ; None ; None ; 3.000 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; bain ; bain ; None ; None ; 3.000 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; bain ; bain ; None ; None ; 3.000 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; cou10:ual|cout ; bain ; bain ; None ; None ; 1.400 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; cou10:ual|cout ; bain ; bain ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; cou10:ual|cout ; bain ; bain ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cou10:ual|lpm_counter:qqout_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; cou10:ual|cout ; bain ; bain ; None ; None ; 1.100 ns ;
+-------+------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'bbin' ;
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