tennis.map.rpt

里面是个乒乓游戏机的试验程序 要的就下载吧 挺好的 用FPGA

+------------------------+-------------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: cou4:ubh|lpm_counter:qqout_rtl_2 ;
+------------------------+-------------------+--------------------------------------+
; Parameter Name         ; Value             ; Type                                 ;
+------------------------+-------------------+--------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                           ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                         ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                         ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                       ;
; LPM_WIDTH              ; 4                 ; Untyped                              ;
; LPM_DIRECTION          ; UP                ; Untyped                              ;
; LPM_MODULUS            ; 0                 ; Untyped                              ;
; LPM_AVALUE             ; UNUSED            ; Untyped                              ;
; LPM_SVALUE             ; UNUSED            ; Untyped                              ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                              ;
; DEVICE_FAMILY          ; ACEX1K            ; Untyped                              ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                              ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                   ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                   ;
; CARRY_CNT_EN           ; SMART             ; Untyped                              ;
; LABWIDE_SCLR           ; ON                ; Untyped                              ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                              ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                              ;
+------------------------+-------------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: cou10:ubl|lpm_counter:qqout_rtl_3 ;
+------------------------+-------------------+---------------------------------------+
; Parameter Name         ; Value             ; Type                                  ;
+------------------------+-------------------+---------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                            ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                          ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                          ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                        ;
; LPM_WIDTH              ; 4                 ; Untyped                               ;
; LPM_DIRECTION          ; UP                ; Untyped                               ;
; LPM_MODULUS            ; 0                 ; Untyped                               ;
; LPM_AVALUE             ; UNUSED            ; Untyped                               ;
; LPM_SVALUE             ; UNUSED            ; Untyped                               ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                               ;
; DEVICE_FAMILY          ; ACEX1K            ; Untyped                               ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                               ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                    ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                    ;
; CARRY_CNT_EN           ; SMART             ; Untyped                               ;
; LABWIDE_SCLR           ; ON                ; Untyped                               ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                               ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                               ;
+------------------------+-------------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Jun 16 17:54:57 2002
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TENNIS -c TENNIS
Info: Found 2 design units, including 1 entities, in source file BALL.VHD
    Info: Found design unit 1: ball-ful
    Info: Found entity 1: ball
Info: Found 2 design units, including 1 entities, in source file BALLCTRL.VHD
    Info: Found design unit 1: ballctrl-ful
    Info: Found entity 1: ballctrl
Info: Found 2 design units, including 1 entities, in source file BOARD.VHD
    Info: Found design unit 1: board-ful
    Info: Found entity 1: board
Info: Found 2 design units, including 1 entities, in source file COU10.VHD
    Info: Found design unit 1: cou10-ful
    Info: Found entity 1: cou10
Info: Found 2 design units, including 1 entities, in source file COU4.VHD
    Info: Found design unit 1: cou4-ful
    Info: Found entity 1: cou4
Info: Found 2 design units, including 1 entities, in source file MWAY.VHD
    Info: Found design unit 1: mway-ful
    Info: Found entity 1: mway
Info: Found 2 design units, including 1 entities, in source file SOUND.VHD
    Info: Found design unit 1: sound-ful
    Info: Found entity 1: sound
Info: Found 2 design units, including 1 entities, in source file TENNIS.VHD
    Info: Found design unit 1: TENNIS-ful
    Info: Found entity 1: TENNIS
Info: Elaborating entity "TENNIS" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at TENNIS.VHD(48): object "cah" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at TENNIS.VHD(48): object "cbh" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at TENNIS.VHD(49): object "serclk" assigned a value but never read
Info: Elaborating entity "cou4" for hierarchy "cou4:uah"
Warning (10492): VHDL Process Statement warning at COU4.VHD(31): signal "qqout" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "cou10" for hierarchy "cou10:ual"
Warning (10492): VHDL Process Statement warning at COU10.VHD(30): signal "qqout" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "board" for hierarchy "board:ubda"
Info: Elaborating entity "ballctrl" for hierarchy "ballctrl:ucpu"
Warning (10492): VHDL Process Statement warning at BALLCTRL.VHD(33): signal "ser" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at BALLCTRL.VHD(25): inferring latch(es) for signal or variable "serve", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at BALLCTRL.VHD(25): inferring latch(es) for signal or variable "ballen", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at BALLCTRL.VHD(25): inferred latch for "ballen"
Info (10041): Verilog HDL or VHDL info at BALLCTRL.VHD(25): inferred latch for "serve"
Info: Elaborating entity "mway" for hierarchy "mway:uway"
Warning (10631): VHDL Process Statement warning at MWAY.VHD(11): inferring latch(es) for signal or variable "way", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at MWAY.VHD(11): inferred latch for "way"
Info: Elaborating entity "ball" for hierarchy "ball:uball"
Warning (10492): VHDL Process Statement warning at BALL.VHD(29): signal "lamp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "sound" for hierarchy "sound:usound"
Info: Inferred 4 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cou4:uah|qqout[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cou10:ual|qqout[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cou4:ubh|qqout[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cou10:ubl|qqout[0]~4"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "cou4:uah|lpm_counter:qqout_rtl_0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "cou4:uah|lpm_counter:qqout_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "cou4:uah|lpm_counter:qqout_rtl_0"
Info: Instantiated megafunction "cou4:uah|lpm_counter:qqout_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Registers with preset signals will power-up high
Info: Implemented 78 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 26 output pins
    Info: Implemented 47 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Sun Jun 16 17:55:00 2002
    Info: Elapsed time: 00:00:03