signal1.vhd

讲述了VHDL语言的基本应用

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity signal1 is
port(clk:in std_logic;
     sync:in std_logic;
     out1:out std_logic;
     out2:out std_logic;
     out3:out std_logic;
     out4:out std_logic);
end signal1;
architecture arc of signal1 is
signal count0,count1,count2,count3,count4:integer;
signal syn:std_logic;

begin
  s:process(sync)
  begin
  if sync'event and sync='0' then
     syn<='1';
  end if;
  end process s;

  a:process(clk)
  begin
  if clk'event and clk='1' then
     if syn='1' then
        if count1<1000 then
           if count1>=230 and count1<270 then
              out1<='1';
           else
              out1<='0';
           end if;
           count1<=count1+1;
        else
           count1<=0;
        end if;
      else
        out1<='0';
      end if;
  end if;
  end process a;
  
  b:process(clk)
  begin
  if clk'event and clk='1' then
     if syn='1' then
        if count2<1000 then
           if count2>=470 and count2<510 then
              out2<='1';
       
              
           else
              out2<='0';
           end if;
           count2<=count2+1;
        else
           count2<=0;
        end if;
     else
        out2<='0';
     end if;
  end if;
  end process b;
  
  c:process(clk)
  begin
  if clk'event and clk='1' then
     if syn='1' then
        if count3<1000 then
           if count3>=710 and count3<750 then
              out3<='1';
           else
              out3<='0';
           end if;
           count3<=count3+1;
        else
           count3<=0;
        end if;
     else
        out3<='0';
     end if;
  end if;
  end process c;

d:process(clk)
begin
if clk'event and clk='1' then
     if syn='1' then
       if count4<=3001 then
          if count4<280 then
               out4<='1';
           else
               out4<='0';
          end if;
          count4<=count4+1;
        else
               count4<=0;
       end if;
    else
        out4<='0';
   end if;
end if;
end process d;
end arc;