📄 sh1.rpt
字号:
- 1 - A 22 AND2 s 0 4 0 2 |SIGNAL1:10|~2897~7
- 7 - A 23 OR2 s 0 4 0 1 |SIGNAL1:10|~2897~8
- 8 - A 23 AND2 0 4 0 1 |SIGNAL1:10|:2897
- 2 - F 09 OR2 0 4 0 33 |SIGNAL1:10|:3768
- 3 - F 19 AND2 s 0 4 0 1 |SIGNAL1:10|~3770~1
- 5 - F 13 AND2 s 0 4 0 1 |SIGNAL1:10|~3770~2
- 1 - E 13 AND2 s 0 4 0 1 |SIGNAL1:10|~3770~3
- 2 - F 24 AND2 s 0 3 0 1 |SIGNAL1:10|~3770~4
- 8 - E 13 AND2 s 0 4 0 1 |SIGNAL1:10|~3770~5
- 3 - F 14 AND2 s 0 4 0 1 |SIGNAL1:10|~3770~6
- 2 - F 19 AND2 s 0 4 0 2 |SIGNAL1:10|~3770~7
- 2 - F 08 OR2 s 0 3 0 2 |SIGNAL1:10|~3882~1
- 1 - F 09 OR2 s 0 4 0 1 |SIGNAL1:10|~3882~2
- 8 - F 09 OR2 ! 0 4 0 1 |SIGNAL1:10|:4223
- 7 - F 09 AND2 ! 0 2 0 1 |SIGNAL1:10|:4241
- 5 - F 09 OR2 0 4 0 1 |SIGNAL1:10|:4422
- 6 - F 09 OR2 s 0 4 0 1 |SIGNAL1:10|~4636~1
- 4 - F 09 AND2 0 4 0 1 |SIGNAL1:10|:4636
- 6 - A 02 OR2 ! 0 4 0 33 |SIGNAL1:10|:5509
- 1 - A 07 AND2 s 0 4 0 1 |SIGNAL1:10|~5516~1
- 2 - A 11 AND2 s 0 4 0 1 |SIGNAL1:10|~5516~2
- 5 - A 03 AND2 s 0 4 0 1 |SIGNAL1:10|~5516~3
- 2 - C 05 AND2 s 0 4 0 1 |SIGNAL1:10|~5516~4
- 2 - C 12 AND2 s 0 4 0 1 |SIGNAL1:10|~5516~5
- 3 - A 02 AND2 s 0 4 0 2 |SIGNAL1:10|~5516~6
- 5 - A 02 OR2 ! 0 4 0 1 |SIGNAL1:10|:5616
- 3 - A 08 OR2 s 0 3 0 1 |SIGNAL1:10|~5618~1
- 4 - A 02 OR2 ! 0 4 0 1 |SIGNAL1:10|:5638
- 8 - A 02 OR2 0 4 0 1 |SIGNAL1:10|:5798
- 6 - A 08 OR2 s 0 4 0 1 |SIGNAL1:10|~5800~1
- 3 - A 06 AND2 0 4 0 1 |SIGNAL1:10|:5919
- 4 - A 06 OR2 0 2 0 2 |SIGNAL1:10|:5937
- 1 - F 05 OR2 0 2 0 8 :3
- 3 - F 02 OR2 0 2 0 136 :92
- 6 - F 01 DFFE 0 1 0 4 |74160:8|QA (|74160:8|:6)
- 1 - F 01 DFFE 0 3 0 2 |74160:8|QB (|74160:8|:7)
- 5 - F 01 DFFE 0 3 0 1 |74160:8|QC (|74160:8|:8)
- 7 - F 01 DFFE 0 4 0 2 |74160:8|QD (|74160:8|:9)
- 2 - F 01 OR2 ! 0 2 0 4 |74160:8|RCO (|74160:8|:45)
- 4 - F 05 DFFE + 0 1 0 4 |74160:9|QA (|74160:9|:6)
- 3 - F 05 DFFE + 0 3 0 2 |74160:9|QB (|74160:9|:7)
- 5 - F 05 DFFE + 0 3 0 2 |74160:9|QC (|74160:9|:8)
- 2 - F 05 DFFE + 0 4 0 1 |74160:9|QD (|74160:9|:9)
- 7 - F 02 DFFE 0 2 0 4 |74160:91|QA (|74160:91|:6)
- 8 - F 02 DFFE 0 4 0 3 |74160:91|QB (|74160:91|:7)
- 2 - F 02 DFFE 0 4 0 1 |74160:91|QC (|74160:91|:8)
- 6 - F 02 DFFE 0 5 0 1 |74160:91|QD (|74160:91|:9)
- 3 - F 01 DFFE 0 1 0 4 |74161:88|f74161:sub|QA (|74161:88|f74161:sub|:9)
- 4 - F 01 DFFE 0 2 0 3 |74161:88|f74161:sub|QB (|74161:88|f74161:sub|:87)
- 5 - F 02 DFFE 0 3 0 2 |74161:88|f74161:sub|QC (|74161:88|f74161:sub|:99)
- 1 - F 02 OR2 ! 0 4 0 4 |74161:88|f74161:sub|:104
- 4 - F 02 DFFE 0 4 0 1 |74161:88|f74161:sub|QD (|74161:88|f74161:sub|:110)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\5.5\sh1.rpt
sh1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 17/ 96( 17%) 22/ 48( 45%) 20/ 48( 41%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 10/ 48( 20%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 2/ 96( 2%) 0/ 48( 0%) 13/ 48( 27%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 17/ 96( 17%) 15/ 48( 31%) 6/ 48( 12%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 14/ 96( 14%) 20/ 48( 41%) 10/ 48( 20%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 6/24( 25%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 6/24( 25%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\5.5\sh1.rpt
sh1
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 136 :92
LCELL 8 :3
INPUT 4 clk
LCELL 4 |74160:8|RCO
LCELL 4 |74161:88|f74161:sub|:104
INPUT 1 data
Device-Specific Information: d:\5.5\sh1.rpt
sh1
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 136 :92
LCELL 8 :3
Device-Specific Information: d:\5.5\sh1.rpt
sh1
** EQUATIONS **
clk : INPUT;
data : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = !_LC7_E24;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = !_LC6_A23;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = !_LC1_A12;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC1_A2;
-- Node name is '|⌨️ 快捷键说明
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