📄 sh1.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\5.5\sh1.rpt
sh1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
205 - - - 24 OUTPUT 0 1 0 0 a
206 - - - 24 OUTPUT 0 1 0 0 b
207 - - A -- OUTPUT 0 1 0 0 c
208 - - A -- OUTPUT 0 1 0 0 d
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\5.5\sh1.rpt
sh1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - E 02 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:167
- 4 - E 02 AND2 0 3 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:171
- 5 - E 24 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:175
- 6 - E 24 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:179
- 1 - E 24 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:183
- 5 - E 03 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:187
- 6 - E 03 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:191
- 7 - E 03 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:195
- 1 - E 03 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:199
- 3 - E 09 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:203
- 4 - E 09 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:207
- 8 - E 09 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:211
- 2 - E 08 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:215
- 2 - E 01 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:219
- 3 - E 01 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:223
- 6 - E 01 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:227
- 1 - E 05 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:231
- 3 - E 05 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:235
- 5 - E 05 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:239
- 4 - E 05 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:243
- 3 - F 07 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:247
- 4 - F 07 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:251
- 5 - F 07 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:255
- 6 - F 04 AND2 0 2 0 4 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:259
- 7 - F 04 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:263
- 8 - F 04 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:267
- 1 - F 04 AND2 0 4 0 4 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:271
- 5 - F 11 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:275
- 7 - F 11 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:279
- 1 - F 11 AND2 0 4 0 1 |SIGNAL1:10|LPM_ADD_SUB:1018|addcore:adder|:283
- 5 - A 20 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:167
- 8 - A 20 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:171
- 1 - A 20 AND2 0 4 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:175
- 7 - A 17 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:179
- 8 - A 17 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:183
- 3 - A 21 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:187
- 4 - A 21 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:191
- 5 - A 21 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:195
- 1 - A 23 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:199
- 3 - A 22 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:203
- 5 - A 22 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:207
- 4 - A 22 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:211
- 1 - A 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:215
- 3 - A 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:219
- 4 - A 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:223
- 2 - A 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:227
- 4 - D 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:231
- 4 - D 16 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:235
- 5 - D 16 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:239
- 1 - D 16 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:243
- 2 - D 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:247
- 5 - D 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:251
- 8 - D 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:255
- 3 - D 19 AND2 0 2 0 4 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:259
- 4 - D 19 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:263
- 8 - D 19 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:267
- 1 - D 19 AND2 0 4 0 4 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:271
- 5 - D 24 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:275
- 7 - D 24 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:279
- 1 - D 24 AND2 0 4 0 1 |SIGNAL1:10|LPM_ADD_SUB:2757|addcore:adder|:283
- 8 - A 12 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:167
- 4 - A 12 AND2 0 3 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:171
- 4 - F 06 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:175
- 6 - F 06 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:179
- 7 - F 06 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:183
- 1 - F 06 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:187
- 1 - F 08 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:191
- 5 - F 08 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:195
- 3 - F 08 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:199
- 1 - F 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:203
- 2 - F 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:207
- 3 - F 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:211
- 8 - F 13 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:215
- 4 - F 19 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:219
- 5 - F 19 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:223
- 1 - F 19 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:227
- 8 - F 24 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:231
- 2 - F 14 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:235
- 5 - F 14 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:239
- 4 - F 14 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:243
- 4 - F 24 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:247
- 5 - F 24 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:251
- 1 - F 24 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:255
- 1 - E 18 AND2 0 2 0 4 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:259
- 5 - E 18 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:263
- 8 - E 18 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:267
- 2 - E 18 AND2 0 4 0 4 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:271
- 4 - E 13 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:275
- 6 - E 13 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:279
- 2 - E 13 AND2 0 4 0 1 |SIGNAL1:10|LPM_ADD_SUB:4496|addcore:adder|:283
- 7 - A 02 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:167
- 3 - A 12 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:171
- 4 - A 17 AND2 0 4 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:175
- 5 - A 06 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:179
- 7 - A 06 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:183
- 1 - A 06 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:187
- 1 - A 08 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:191
- 5 - A 08 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:195
- 2 - A 08 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:199
- 6 - A 04 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:203
- 7 - A 04 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:207
- 8 - A 04 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:211
- 4 - A 04 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:215
- 2 - A 03 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:219
- 4 - A 03 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:223
- 1 - A 03 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:227
- 1 - A 11 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:231
- 3 - A 11 AND2 0 2 0 2 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:235
- 8 - A 11 AND2 0 2 0 4 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:239
- 4 - A 07 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:243
- 6 - A 07 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:247
- 2 - A 07 AND2 0 4 0 4 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:251
- 4 - C 05 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:255
- 6 - C 05 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:259
- 1 - C 05 AND2 0 4 0 4 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:263
- 4 - C 06 AND2 0 2 0 1 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:267
- 1 - C 06 AND2 0 3 0 1 |SIGNAL1:10|LPM_ADD_SUB:6007|addcore:adder|:271
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