📄 sh1.rpt
字号:
VCCINT | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
RESERVED | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | VCCINT
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
VCCINT | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
data | 47 110 | VCCIO
GNDIO | 48 109 | VCCINT
GNDINT | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R R G R R R V V G G G G G R V R R R R R R G R R R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E E N E E E C C N N N N N E C E E E E E E N E E E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S S D S S S C C D D D D D S C S S S S S S D S S S S S S C S S S S S S
E E E E E E I E E E E E E I E E E E E I E E E I I I I I I I E I E E E E E E I E E E E E E I E E E E E E
R R R R R R O R R R R R R O R R R R R O R R R N N N N N N N R O R R R R R R O R R R R R R O R R R R R R
V V V V V V V V V V V V V V V V V V V V T T T T T T T V V V V V V V V V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\5.5\sh1.rpt
sh1
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 16/22( 72%)
A3 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
A4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
A6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
A7 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
A8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A11 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
A12 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
A13 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
A17 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 8/22( 36%)
A20 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
A21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
A22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
A23 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
C5 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
C6 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C12 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 8/22( 36%)
D13 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
D16 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
D19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
D24 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 8/22( 36%)
E1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
E2 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
E3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
E5 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
E7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
E8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
E12 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 13/22( 59%)
E13 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 8/22( 36%)
E18 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
E24 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
F1 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 2/2 0/2 1/22( 4%)
F2 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 3/22( 13%)
F4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
F5 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 0/22( 0%)
F6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
F7 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
F8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
F9 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
F11 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 8/22( 36%)
F13 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
F14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
F19 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
F20 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F24 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 5/141 ( 3%)
Total logic cells used: 332/1152 ( 28%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.24/4 ( 81%)
Total fan-in: 1077/4608 ( 23%)
Total input pins required: 2
Total input I/O cell registers required: 0
Total output pins required: 4
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 332
Total flipflops required: 149
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 43/1152 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 8 7 8 0 8 7 8 0 0 7 8 0 8 0 0 0 8 0 0 8 8 8 8 0 109/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 7 4 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 19/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 8 0 0 8 0 0 0 0 8 32/0
E: 8 7 8 0 8 0 1 1 8 0 0 8 0 8 0 0 0 0 8 0 0 0 0 0 7 72/0
F: 7 8 0 8 5 8 7 8 8 0 8 0 0 8 8 0 0 0 0 8 1 0 0 0 8 100/0
Total: 15 23 15 16 20 20 15 17 16 0 15 24 0 32 8 0 8 8 8 16 9 8 8 8 23 332/0
Device-Specific Information: d:\5.5\sh1.rpt
sh1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
183 - - - -- INPUT G 0 0 0 0 clk
47 - - F -- INPUT 0 0 0 1 data
Code:
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