📄 signal1.rpt
字号:
- 3 - B 20 DFFE + 0 3 0 4 count426 (:113)
- 6 - B 17 DFFE + 0 3 0 2 count425 (:114)
- 3 - B 17 DFFE + 0 3 0 3 count424 (:115)
- 7 - B 17 DFFE + 0 3 0 4 count423 (:116)
- 6 - B 22 DFFE + 0 3 0 2 count422 (:117)
- 4 - B 22 DFFE + 0 3 0 3 count421 (:118)
- 1 - B 22 DFFE + 0 3 0 4 count420 (:119)
- 8 - B 16 DFFE + 0 3 0 2 count419 (:120)
- 7 - B 16 DFFE + 0 3 0 2 count418 (:121)
- 6 - B 16 DFFE + 0 3 0 2 count417 (:122)
- 1 - B 15 DFFE + 0 3 0 2 count416 (:123)
- 8 - B 15 DFFE + 0 3 0 2 count415 (:124)
- 7 - B 15 DFFE + 0 3 0 2 count414 (:125)
- 6 - B 15 DFFE + 0 3 0 2 count413 (:126)
- 6 - B 24 DFFE + 0 3 0 2 count412 (:127)
- 6 - B 21 DFFE + 0 3 0 3 count411 (:128)
- 3 - B 21 DFFE + 0 3 0 3 count410 (:129)
- 5 - B 21 DFFE + 0 3 0 3 count49 (:130)
- 4 - B 21 DFFE + 0 3 0 3 count48 (:131)
- 5 - B 19 DFFE + 0 3 0 3 count47 (:132)
- 6 - B 19 DFFE + 0 3 0 3 count46 (:133)
- 6 - B 13 DFFE + 0 3 0 3 count45 (:134)
- 2 - B 13 DFFE + 0 3 0 2 count44 (:135)
- 5 - B 13 DFFE + 0 3 0 2 count43 (:136)
- 8 - B 17 DFFE + 0 3 0 3 count42 (:137)
- 1 - B 20 DFFE + 0 3 0 4 count41 (:138)
- 2 - B 20 DFFE + 0 2 0 4 count40 (:139)
- 1 - C 11 OR2 0 4 0 33 :290
- 2 - C 16 AND2 s 0 4 0 1 ~292~1
- 3 - C 17 AND2 s 0 4 0 1 ~292~2
- 2 - C 21 AND2 s 0 4 0 1 ~292~3
- 1 - C 13 AND2 s 0 3 0 1 ~292~4
- 1 - C 21 AND2 s 0 4 0 1 ~292~5
- 3 - C 18 AND2 s 0 4 0 1 ~292~6
- 2 - C 11 AND2 s 0 4 0 2 ~292~7
- 4 - C 10 OR2 s 0 3 0 2 ~404~1
- 3 - C 11 OR2 s 0 4 0 1 ~404~2
- 3 - C 07 OR2 0 2 0 1 :763
- 3 - C 10 AND2 s 0 4 0 1 ~1397~1
- 5 - C 11 OR2 s 0 4 0 1 ~1397~2
- 4 - C 07 OR2 s 0 4 0 1 ~1397~3
- 7 - C 11 OR2 s 0 4 0 1 ~1397~4
- 8 - C 11 AND2 s 0 4 0 1 ~1397~5
- 8 - A 16 OR2 0 4 0 33 :2029
- 8 - A 17 OR2 s 0 3 0 2 ~2143~1
- 1 - A 16 OR2 s 0 4 0 1 ~2143~2
- 1 - A 13 OR2 ! 0 4 0 1 :2492
- 2 - A 13 OR2 s 0 4 0 1 ~2681~1
- 5 - A 21 AND2 s 0 4 0 1 ~2897~1
- 3 - A 22 AND2 s 0 4 0 1 ~2897~2
- 2 - A 23 AND2 s 0 4 0 1 ~2897~3
- 2 - A 15 AND2 s 0 3 0 1 ~2897~4
- 1 - A 23 AND2 s 0 4 0 1 ~2897~5
- 2 - A 18 AND2 s 0 4 0 1 ~2897~6
- 1 - A 22 AND2 s 0 4 0 2 ~2897~7
- 7 - A 16 OR2 s 0 4 0 1 ~2897~8
- 3 - A 16 AND2 0 4 0 1 :2897
- 1 - F 23 OR2 0 4 0 33 :3768
- 5 - F 09 AND2 s 0 4 0 1 ~3770~1
- 1 - F 17 AND2 s 0 4 0 1 ~3770~2
- 3 - F 02 AND2 s 0 4 0 1 ~3770~3
- 1 - F 10 AND2 s 0 3 0 1 ~3770~4
- 1 - F 02 AND2 s 0 4 0 1 ~3770~5
- 4 - F 01 AND2 s 0 4 0 1 ~3770~6
- 2 - F 23 AND2 s 0 4 0 2 ~3770~7
- 3 - F 15 OR2 s 0 3 0 2 ~3882~1
- 3 - F 23 OR2 s 0 4 0 1 ~3882~2
- 6 - F 23 OR2 ! 0 4 0 1 :4223
- 3 - F 13 AND2 ! 0 2 0 1 :4241
- 2 - F 13 OR2 0 4 0 1 :4422
- 5 - F 23 OR2 s 0 4 0 1 ~4636~1
- 7 - F 23 AND2 0 4 0 1 :4636
- 3 - B 24 OR2 ! 0 4 0 33 :5509
- 2 - B 22 AND2 s 0 4 0 1 ~5516~1
- 5 - B 16 AND2 s 0 4 0 1 ~5516~2
- 2 - B 15 AND2 s 0 4 0 1 ~5516~3
- 3 - B 23 AND2 s 0 4 0 1 ~5516~4
- 1 - B 23 AND2 s 0 4 0 1 ~5516~5
- 2 - B 24 AND2 s 0 4 0 2 ~5516~6
- 1 - B 19 OR2 ! 0 4 0 1 :5616
- 3 - B 19 OR2 s 0 3 0 1 ~5618~1
- 4 - B 13 OR2 ! 0 4 0 1 :5638
- 5 - B 24 OR2 0 4 0 1 :5798
- 2 - B 19 OR2 s 0 4 0 1 ~5800~1
- 7 - B 19 AND2 0 4 0 1 :5919
- 3 - B 13 OR2 0 2 0 2 :5937
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\5.5\signal1.rpt
signal1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 28/ 48( 58%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 36/ 48( 75%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 8/ 96( 8%) 13/ 48( 27%) 13/ 48( 27%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 7/ 96( 7%) 12/ 48( 25%) 14/ 48( 29%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\5.5\signal1.rpt
signal1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 132 clk
INPUT 1 sync
Device-Specific Information: d:\5.5\signal1.rpt
signal1
** EQUATIONS **
clk : INPUT;
sync : INPUT;
-- Node name is ':43' = 'count10'
-- Equation name is 'count10', location is LC5_C7, type is buried.
count10 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !count10 & _LC1_C11 & syn
# count10 & !syn;
-- Node name is ':42' = 'count11'
-- Equation name is 'count11', location is LC6_C7, type is buried.
count11 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !count10 & count11 & _LC1_C11
# count10 & !count11 & _LC1_C11 & syn
# count11 & !syn;
-- Node name is ':41' = 'count12'
-- Equation name is 'count12', location is LC8_C7, type is buried.
count12 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = count12 & _LC1_C11 & !_LC7_C7
# !count12 & _LC1_C11 & _LC7_C7 & syn
# count12 & !syn;
-- Node name is ':40' = 'count13'
-- Equation name is 'count13', location is LC2_C7, type is buried.
count13 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = count13 & !_LC1_C7 & _LC1_C11
# !count13 & _LC1_C7 & _LC1_C11 & syn
# count13 & !syn;
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