i8051_ctr.vhd

8051 VHDL IP Core

                                    alu_src_1 <= reg_acc;
                                    alu_src_2 <= ram_in_data;
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    ram_out_data <= alu_des_1;
                                    START_WR_RAM(R_ACC);
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- acc <- acc && ((r))
                        --
                        when OPC_ANL_3  =>
                            case exe_state is
                                when ES_0 =>
                                    GET_RAM_ADDR_2(v8);
                                    START_RD_RAM(v8);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    START_RD_RAM(ram_in_data);
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    alu_op_code <= ALU_OPC_AND;
                                    alu_src_1 <= reg_acc;
                                    alu_src_2 <= ram_in_data;
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    ram_out_data <= alu_des_1;
                                    START_WR_RAM(R_ACC);
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- acc <- acc && #data
                        --
                        when OPC_ANL_4  =>
                            case exe_state is
                                when ES_0 =>
                                    alu_op_code <= ALU_OPC_AND;
                                    alu_src_1 <= reg_acc;
                                    alu_src_2 <= reg_op2;
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    ram_out_data <= alu_des_1;
                                    START_WR_RAM(R_ACC);
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- (direct) <- (direct) && acc
                        --
                        when OPC_ANL_5  =>
                            case exe_state is
                                when ES_0 =>
                                    START_RD_RAM(reg_op2);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    alu_op_code <= ALU_OPC_AND;
                                    alu_src_1 <= reg_acc;
                                    alu_src_2 <= ram_in_data;
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    ram_out_data <= alu_des_1;
                                    START_WR_RAM(reg_op2);
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- (direct) <- (direct) && #data
                        --
                        when OPC_ANL_6  =>
                            case exe_state is
                                when ES_0 =>
                                    START_RD_RAM(reg_op2);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    alu_op_code <= ALU_OPC_AND;
                                    alu_src_1 <= reg_op3;
                                    alu_src_2 <= ram_in_data;
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    ram_out_data <= alu_des_1;
                                    START_WR_RAM(reg_op2);
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- cy <- cy & (bit)
                        --
                        when OPC_ANL_7  =>
                            case exe_state is
                                when ES_0 =>
                                    START_RD_BIT_RAM(reg_op2);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    reg_cy <= reg_cy and ram_in_bit_data;
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    GET_PSW(v8);
                                    ram_out_data <= v8;
                                    START_WR_RAM(R_PSW);
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- cy <- cy & ~(bit)
                        --
                        when OPC_ANL_8  =>
                            case exe_state is
                                when ES_0 =>
                                    START_RD_BIT_RAM(reg_op2);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    reg_cy <= reg_cy and (not ram_in_bit_data);
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    GET_PSW(v8);
                                    ram_out_data <= v8;
                                    START_WR_RAM(R_PSW);
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- if( a != (direct) )
                        --     pc <- pc + rel
                        -- if( a < (direct) )
                        --     cy <- 1
                        -- else
                        --     cy <- 0
                        --
                        when OPC_CJNE_1 =>
                            case exe_state is
                                when ES_0 =>
                                    START_RD_RAM(reg_op2);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    GET_PC_H(pch);
                                    GET_PC_L(pcl);
                                    alu_op_code <= ALU_OPC_PCSADD;
                                    alu_src_1 <= pcl;
                                    alu_src_2 <= pch;
                                    if( reg_acc /= ram_in_data ) then

                                        alu_src_3 <= reg_op3;
                                    else

                                        alu_src_3 <= C0_8;
                                    end if;
                                    if( reg_acc < ram_in_data ) then

                                        reg_cy <= '1';
                                    else

                                        reg_cy <= '0';
                                    end if;
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    SET_PC_1(alu_des_2, alu_des_1);
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    GET_PSW(v8);
                                    ram_out_data <= v8;
                                    START_WR_RAM(R_PSW);
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- if( a != #data )
                        --     pc <- pc + rel
                        -- if( a < #data )
                        --     cy <- 1
                        -- else
                        --     cy <- 0