i8051_ctr.vhd

8051 VHDL IP Core

            STOP_RD_WR_RAM;
            STOP_RD_WR_XRM;
            SHUT_DOWN_ALU;
            
        elsif( clk'event and clk = '1' ) then

            STOP_RD_ROM;
            STOP_RD_WR_RAM;
            STOP_RD_WR_XRM;
            
            case cpu_state is

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

                --
                -- reset controller
                --
                when CS_0 =>
                    case exe_state is
                        when ES_0 =>
                            ram_out_data <= CM_8;
                            START_WR_RAM(R_P0);
                            exe_state <= ES_1;

                        when ES_1 =>
                            ram_out_data <= CM_8;
                            START_WR_RAM(R_P1);
                            exe_state <= ES_2;

                        when ES_2 =>
                            ram_out_data <= CM_8;
                            START_WR_RAM(R_P2);
                            exe_state <= ES_3;

                        when ES_3 =>
                            ram_out_data <= CM_8;
                            START_WR_RAM(R_P3);
                            exe_state <= ES_4;

                        when ES_4 =>
                            ram_out_data <= C7_8;
                            START_WR_RAM(R_SP);
                            exe_state <= ES_5;

                        when ES_5 =>
                            cpu_state <= CS_1;
                            exe_state <= ES_0;

                        when others => null;
                    end case;

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

                --
                -- handle interrupts
                --
                when CS_1 =>
                    cpu_state <= CS_2;

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

                --
                -- process instructions
                --
                when CS_2 =>
                    case exe_state is
                        when ES_0 =>
                            GET_PC_H(pch);
                            GET_PC_L(pcl);
                            START_RD_ROM(pch, pcl);
                            alu_op_code <= ALU_OPC_PCUADD;
                            alu_src_1 <= pcl;
                            alu_src_2 <= pch;
                            alu_src_3 <= C1_8;
                            exe_state <= ES_1;

                        when ES_1 =>
                            START_RD_RAM(R_PSW);
                            exe_state <= ES_2;

                        when ES_2 =>
                            START_RD_RAM(R_ACC);
                            reg_op1 <= rom_data;
                            exe_state <= ES_3;
                            
                        when ES_3 =>
                            START_RD_ROM(alu_des_2, alu_des_1);
                            SET_PSW(ram_in_data);
                            alu_op_code <= ALU_OPC_PCUADD;
                            alu_src_1 <= alu_des_1;
                            alu_src_2 <= alu_des_2;
                            if( dec_op_in(7) = '1' ) then

                                alu_src_3 <= C1_8;
                            else

                                alu_src_3 <= C0_8;
                            end if;
                            exe_state <= ES_4;

                        when ES_4 =>
                            START_RD_ROM(alu_des_2, alu_des_1);
                            reg_acc <= ram_in_data;
                            alu_op_code <= ALU_OPC_PCUADD;
                            alu_src_1 <= alu_des_1;
                            alu_src_2 <= alu_des_2;
                            if( dec_op_in(8) = '1' ) then

                                alu_src_3 <= C1_8;
                            else

                                alu_src_3 <= C0_8;
                            end if;
                            exe_state <= ES_5;

                        when ES_5 =>
                            reg_op2 <= rom_data;
                            SET_PC_1(alu_des_2, alu_des_1);
                            exe_state <= ES_6;

                        when ES_6 =>
                            reg_op3 <= rom_data;
                            exe_state <= ES_7;

                        when ES_7 =>
                            SHUT_DOWN_ALU;
                            cpu_state <= CS_3;
                            exe_state <= ES_0;
                    end case;

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
                    
                --
                -- execute state
                --
                when CS_3 =>
                    case dec_op_in(6 downto 0) is

-------------------------------------------------------------------------------

                        --
                        -- sp       <- sp + 1
                        -- mem(sp)  <- pc(7-0)
                        -- sp       <- sp + 1
                        -- mem(sp)  <- pc(15-8)
                        -- pc(10-0) <- page address
                        --
                        when OPC_ACALL  =>
                            case exe_state is
                                when ES_0 =>
                                    START_RD_RAM(R_SP);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    alu_op_code <= ALU_OPC_ADD;
                                    alu_src_1 <= ram_in_data;
                                    alu_src_2 <= C0_8;
                                    alu_src_cy <= '1';
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    GET_PC_L(pcl);
                                    alu_op_code <= ALU_OPC_ADD;
                                    alu_src_1 <= alu_des_1;
                                    alu_src_2 <= C0_8;
                                    alu_src_cy <= '1';
                                    ram_out_data <= pcl;
                                    START_WR_RAM(alu_des_1);
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    GET_PC_H(pch);
                                    ram_out_data <= pch;
                                    START_WR_RAM(alu_des_1);
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    ram_out_data <= alu_des_1;
                                    START_WR_RAM(R_SP);
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    SET_PC_2(reg_op1(7 downto 5), reg_op2);
                                    exe_state <= ES_7;

                               when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- acc <- acc + (r)
                        --
                        when OPC_ADD_1  =>
                            case exe_state is
                                when ES_0 =>
                                    GET_RAM_ADDR_1(v8);
                                    START_RD_RAM(v8);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    alu_op_code <= ALU_OPC_ADD;
                                    alu_src_1 <= reg_acc;
                                    alu_src_2 <= ram_in_data;
                                    alu_src_cy <= '0';
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    ram_out_data <= alu_des_1;
                                    START_WR_RAM(R_ACC);
                                    reg_cy <= alu_des_cy;
                                    reg_ac <= alu_des_ac;
                                    reg_ov <= alu_des_ov;
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    GET_PSW(v8);
                                    ram_out_data <= v8;
                                    START_WR_RAM(R_PSW);
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- acc <- acc + (direct)
                        --
                        when OPC_ADD_2  =>
                            case exe_state is
                                when ES_0 =>
                                    START_RD_RAM(reg_op2);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    alu_op_code <= ALU_OPC_ADD;
                                    alu_src_1 <= reg_acc;
                                    alu_src_2 <= ram_in_data;
                                    alu_src_cy <= '0';
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    ram_out_data <= alu_des_1;
                                    START_WR_RAM(R_ACC);
                                    reg_cy <= alu_des_cy;
                                    reg_ac <= alu_des_ac;
                                    reg_ov <= alu_des_ov;
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    GET_PSW(v8);
                                    ram_out_data <= v8;
                                    START_WR_RAM(R_PSW);
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    exe_state <= ES_7;

                                when ES_7 =>
                                    SHUT_DOWN_ALU;
                                    cpu_state <= CS_1;
                                    exe_state <= ES_0;
                            end case;

-------------------------------------------------------------------------------

                        --
                        -- acc <- acc + ((r))
                        --
                        when OPC_ADD_3  =>
                            case exe_state is
                                when ES_0 =>
                                    GET_RAM_ADDR_2(v8);
                                    START_RD_RAM(v8);
                                    exe_state <= ES_1;

                                when ES_1 =>
                                    exe_state <= ES_2;

                                when ES_2 =>
                                    START_RD_RAM(ram_in_data);
                                    exe_state <= ES_3;

                                when ES_3 =>
                                    exe_state <= ES_4;

                                when ES_4 =>
                                    alu_op_code <= ALU_OPC_ADD;
                                    alu_src_1 <= reg_acc;
                                    alu_src_2 <= ram_in_data;
                                    alu_src_cy <= '0';
                                    exe_state <= ES_5;

                                when ES_5 =>
                                    ram_out_data <= alu_des_1;
                                    START_WR_RAM(R_ACC);
                                    reg_cy <= alu_des_cy;
                                    reg_ac <= alu_des_ac;
                                    reg_ov <= alu_des_ov;
                                    exe_state <= ES_6;

                                when ES_6 =>
                                    GET_PSW(v8);
                                    ram_out_data <= v8;
                                    START_WR_RAM(R_PSW);
                                    exe_state <= ES_7;