i8051_xrm.vhd

8051 VHDL IP Core

--
-- Copyright (c) 2001 Koay Kah Hoe.  Permission to copy is granted
-- provided that this header remains intact.  This code is provided
-- with no warranties.
--
-- Version : 1.0
--

-------------------------------------------------------------------------------
-- Synthesizable VHDL generated by VHDL Module Generator
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.I8051_LIB.all;

library unisim;
use unisim.VCOMPONENTS.all;

-------------------------------------------------------------------------------

--
-- rst (active hi) : when asserted, the registers are set to default values
-- clk (rising edge) : clock signal - all ram i/o is synchronous
-- addr : this is the address of ram/reg being requested
-- in_data : this is the data being writen into the ram/reg
-- out_data : this is the data being read from the ram/reg
-- rd (active hi) : asserted to signal a ram/reg read
-- wr (active hi) : asserted to signal a ram/reg write
--
entity I8051_XRM is
	generic (
		Blocks: integer := 3 
	);
	port (
		in_data : in UNSIGNED(7 downto 0);
		rd : in STD_LOGIC;
		wr : in STD_LOGIC;
		rst : in STD_LOGIC;
		clk : in STD_LOGIC;
		addr : in UNSIGNED(15 downto 0);
		out_data : out UNSIGNED(7 downto 0)
	);
	type ENUM_Multiplexer is (TristateBuffers, NormalGates);
	constant Multiplexer: ENUM_Multiplexer := TristateBuffers;
end I8051_XRM;

architecture I8051_XRM_arch of I8051_XRM is

	signal DI : UNSIGNED(7 downto 0);
	signal EN : UNSIGNED(Blocks-1 downto 0);
	type RAMOut_Array is array (0 to Blocks-1) of UNSIGNED(out_data'range);
	signal RAMOut : RAMOut_Array;
	signal iA,iA2 : integer;
	signal rdwr : STD_LOGIC;
	signal addr_ltched: UNSIGNED(addr'left downto 9);

	component RAMB4_S8
	port (
		DI : in UNSIGNED (7 downto 0);
		EN : in STD_LOGIC;
		WE : in STD_LOGIC;
		RST : in STD_LOGIC;
		CLK : in STD_LOGIC;
		ADDR : in UNSIGNED (8 downto 0);
		DO : out UNSIGNED (7 downto 0)
	);
	end component;

begin

	rdwr <= rd or wr;

	G1: if Blocks>1 generate

		process (clk)
		begin
			if clk'event and clk='1' then
				if rd = '1' then
					addr_ltched <= addr(addr'left downto 9);
				end if;
			end if;
		end process;

		iA <= CONV_INTEGER(addr(addr'left downto 9));
		iA2 <= CONV_INTEGER(addr_ltched(addr'left downto 9));
		
		-- Convert binary number to one-hot format
		process (iA,rdwr)
			variable S:UNSIGNED (Blocks-1 downto 0);
		begin
			S := CONV_UNSIGNED(1,Blocks);
			for I in 0 to Blocks-1 loop
				if I < iA then
					S := SHL(S,"1");
				end if;
			end loop;
			if rdwr = '0' then
				S := (others=>'0');
			end if;
	
			EN <= CONV_UNSIGNED(S,Blocks);
		end process;
	
		G1_1: for I in 0 to Blocks-1 generate
			-- 512 bytes (0x0000~0x01ff)
			U_RAMB4_S8: RAMB4_S8
				port map (in_data, EN(I), wr, rst, clk, addr(8 downto 0), RAMOut(I));
	
			-- Multiplexer using tristate buffers
			G1_1_1: if Multiplexer=TristateBuffers generate
				out_data <= RAMOut(I) when iA2=I else (others=>'Z');
			end generate;
		end generate;
	
		-- Multiplexer using normal gates
		G1_2: if Multiplexer=NormalGates generate
			process (iA2,RAMOut)
			begin
				out_data <= RAMOut(0);
				for I in 1 to Blocks-1 loop
					if iA2=I then
						out_data <= RAMOut(I);
					end if;
				end loop;
			end process;
		end generate;
	end generate;

	G2: if Blocks=1 generate
		U_RAMB4_S8: RAMB4_S8
			port map (in_data, rdwr, wr, rst, clk, addr(8 downto 0), out_data);
	end generate;

end I8051_XRM_arch;