universe_dy4.h

Curtiss-Wright Controls Embedded Computing公司的cw183板bsp源代码

#define DGCS_VON_512            (2 << 20)       /* Transfer count 512 bytes */
#define DGCS_VON_1024           (3 << 20)       /* Transfer count 1024 bytes */
#define DGCS_VON_2048           (4 << 20)       /* Transfer count 2048 bytes */
#define DGCS_VON_4096           (5 << 20)       /* Transfer count 4096 bytes */
#define DGCS_VON_8192           (6 << 20)       /* Transfer count 4096 bytes */
#define DGCS_VON_16384          (7 << 20)       /* Transfer count 16384 bytes */
#define DGCS_VOFF_0             (0)             /* Time off VME bus0 us */
#define DGCS_VOFF_16            (1 << 16)       /* Time off VME bus16 us */
#define DGCS_VOFF_32            (2 << 16)       /* Time off VME bus32 us */
#define DGCS_VOFF_64            (3 << 16)       /* Time off VME bus64 us */
#define DGCS_VOFF_128           (4 << 16)       /* Time off VME bus128 us */
#define DGCS_VOFF_256           (5 << 16)       /* Time off VME bus256 us */
#define DGCS_VOFF_512           (6 << 16)       /* Time off VME bus512 us */
#define DGCS_VOFF_1024          (7 << 16)       /* Time off VME bus1024 us */
#define DGCS_ACT                (1 << 15)       /* DMA active */
#define DGCS_STOP               (1 << 14)       /* DMA stopped */
#define DGCS_HALT               (1 << 13)       /* DMA halted */
#define DGCS_DONE               (1 << 11)       /* DMA done */
#define DGCS_LERR               (1 << 10)       /* PCI bus error */
#define DGCS_VERR               (1 << 9)        /* VME bus error */
#define DGCS_P_ERR              (1 << 8)        /* Protocol error */
#define DGCS_INT_STOP           (1 << 6)        /* Interrupt stop enable */
#define DGCS_INT_HALT           (1 << 5)        /* Interrupt halt enable */
#define DGCS_INT_DONE           (1 << 3)        /* Interrupt done enable */
#define DGCS_INT_LERR           (1 << 2)        /* Interrupt LERR enable */
#define DGCS_INT_VERR           (1 << 1)        /* Interrupt VERR enable */
#define DGCS_INT_P_ERR          (1)             /* Interrupt protocol enable */

/* DMA Linked List Update Enable Register */

/* PCI Configuration Base Address Register */

#define PCI_BS_SPACE            (1)             /* Memory or I/O power-up */

/* PCI Interrupt Enable Register */

#define LINT_EN_MASK            0xffff0000      /* Reserved bits */
#define LINT_EN_ACFAIL          (1 << 15)       /* Enable Interrupt ACFAIL   */
#define LINT_EN_SYSFAIL         (1 << 14)       /* Enable Interrupt SYSFAIL  */
#define LINT_EN_SW_INT          (1 << 13)       /* Enable Interrupt SW_INT   */
#define LINT_EN_SW_IACK         (1 << 12)       /* Enable Interrupt SW_ACK   */
#define LINT_EN_VERR            (1 << 10)       /* Enable Interrupt ACFAIL   */
#define LINT_EN_LERR            (1 << 9)        /* Enable Interrupt ACFAIL   */
#define LINT_EN_DMA             (1 << 8)        /* Enable Interrupt ACFAIL   */
#define LINT_EN_VIRQ7           (1 << 7)        /* Enable Interrupt VME IRQ7 */
#define LINT_EN_VIRQ6           (1 << 6)        /* Enable Interrupt VME IRQ6 */
#define LINT_EN_VIRQ5           (1 << 5)        /* Enable Interrupt VME IRQ5 */
#define LINT_EN_VIRQ4           (1 << 4)        /* Enable Interrupt VME IRQ4 */
#define LINT_EN_VIRQ3           (1 << 3)        /* Enable Interrupt VME IRQ3 */
#define LINT_EN_VIRQ2           (1 << 2)        /* Enable Interrupt VME IRQ2 */
#define LINT_EN_VIRQ1           (1 << 1)        /* Enable Interrupt VME IRQ1 */
#define LINT_EN_VOWN            (1 << 0)        /* Enable Interrupt VME OWN */

/* PCI Interrupt Status Register */

#define LINT_STAT_MASK          0xffff0800      /* Reserved bits */
#define LINT_STAT_ACFAIL        (1 << 15)       /* Status Interrupt ACFAIL   */
#define LINT_STAT_SYSFAIL       (1 << 14)       /* Status Interrupt SYSFAIL  */
#define LINT_STAT_SW_INT        (1 << 13)       /* Status Interrupt SW_INT   */
#define LINT_STAT_SW_IACK       (1 << 12)       /* Status Interrupt SW_ACK   */
#define LINT_STAT_VERR          (1 << 10)       /* Status Interrupt ACFAIL   */
#define LINT_STAT_LERR          (1 << 9)        /* Status Interrupt ACFAIL   */
#define LINT_STAT_DMA           (1 << 8)        /* Status Interrupt ACFAIL   */
#define LINT_STAT_VIRQ7         (1 << 7)        /* Status Interrupt VME IRQ7 */
#define LINT_STAT_VIRQ6         (1 << 6)        /* Status Interrupt VME IRQ6 */
#define LINT_STAT_VIRQ5         (1 << 5)        /* Status Interrupt VME IRQ5 */
#define LINT_STAT_VIRQ4         (1 << 4)        /* Status Interrupt VME IRQ4 */
#define LINT_STAT_VIRQ3         (1 << 3)        /* Status Interrupt VME IRQ3 */
#define LINT_STAT_VIRQ2         (1 << 2)        /* Status Interrupt VME IRQ2 */
#define LINT_STAT_VIRQ1         (1 << 1)        /* Status Interrupt VME IRQ1 */
#define LINT_STAT_VOWN          (1 << 0)        /* Status Interrupt VME OWN */
#define LINT_STAT_RESET         0xfff7ff        /* Reset LINT_STAT reg*/          
#define LINT_STAT_INT_MASK	0x00fff7ff	/* mask received interrupts */
#define LINT_STAT_FAIL_MASK     0x0000c000      /* mask for sysfail,acfail */

/* PCI Interrupt MAP Register 0 */

#define LINT_MAP0_MASK  0x88888888

/* PCI Interrupt MAP Register 1 */

#define LINT_MAP1_MASK  0x8888f888

/* VMEbus Interrupt Enable Register */

#define VINT_EN_MASK            0xffffe800      /* Reserved bits */
#define VINT_EN_SW_INT          (1 << 12)       /* SW_INT interrupt generate */
#define VINT_EN_VERR            (1 << 10)       /* VERR interrupt generate */
#define VINT_EN_LERR            (1 << 9)        /* LERR enable */
#define VINT_EN_DMA             (1 << 8)        /* DMA enable */
#define VINT_EN_LINT7           (1 << 7)        /* LINT7 enable */
#define VINT_EN_LINT6           (1 << 6)        /* LINT6 enable */
#define VINT_EN_LINT5           (1 << 5)        /* LINT5 enable */
#define VINT_EN_LINT4           (1 << 4)        /* LINT4 enable */
#define VINT_EN_LINT3           (1 << 3)        /* LINT3 enable */
#define VINT_EN_LINT2           (1 << 2)        /* LINT2 enable */
#define VINT_EN_LINT1           (1 << 1)        /* LINT1 enable */
#define VINT_EN_LINT0           (1)             /* LINT0 enable */

/* VMEbus Interrupt Status Register */

#define VINT_STAT_MASK          0xffffe800      /* Reserved bits */
#define VINT_STAT_SW_INT        (1 << 12)       /* SW_INT interrupt active */
#define VINT_STAT_VERR          (1 << 10)       /* VERR interrupt active */
#define VINT_STAT_LERR          (1 << 9)        /* LERR interrupt active */
#define VINT_STAT_DMA           (1 << 8)        /* DMA interrupt active */
#define VINT_STAT_LINT7         (1 << 7)        /* LINT7 interrupt active */
#define VINT_STAT_LINT6         (1 << 6)        /* LINT6 interrupt active */
#define VINT_STAT_LINT5         (1 << 5)        /* LINT5 interrupt active */
#define VINT_STAT_LINT4         (1 << 4)        /* LINT4 interrupt active */
#define VINT_STAT_LINT3         (1 << 3)        /* LINT3 interrupt active */
#define VINT_STAT_LINT2         (1 << 2)        /* LINT2 interrupt active */
#define VINT_STAT_LINT1         (1 << 1)        /* LINT1 interrupt active */
#define VINT_STAT_LINT0         (1)             /* LINT0 interrupt active */
#define VINT_STAT_RESET         0xfef017ff      /* Reset VINT_STAT reg*/
#define VINT_STAT_CLEAR		    0x17ff		    /* clear outgoing VME intrs. */

/* VMEbus Interrupt Map Register 0 */

#define VINT_MAP0_MASK          0x88888888
#define VINT_MAP0_MAPPING		0x76543210

/* VMEbus Interrupt Map Register 1 */

#define VINT_MAP1_MASK          0xfffefeee
#define VINT_MAP1_DMA_MASK      0x07
#define VINT_MAP1_DMA_LVL_1     0x01
#define VINT_MAP1_DMA_LVL_2     0x02
#define VINT_MAP1_DMA_LVL_3     0x03
#define VINT_MAP1_DMA_LVL_4     0x04
#define VINT_MAP1_DMA_LVL_5     0x05
#define VINT_MAP1_DMA_LVL_6     0x06
#define VINT_MAP1_DMA_LVL_7     0x07

/* VMEbus Interrupt Status/ID Out Register */

#define STATID_MASK             0x1ffffff

/* VMEbus IRQ1 Status/ID Register */

#define V1_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ2 Status/ID Register */

#define V2_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ3 Status/ID Register */

#define V3_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ4 Status/ID Register */

#define V4_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ5 Status/ID Register */

#define V5_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ6 Status/ID Register */

#define V6_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ7 Status/ID Register */

#define V7_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus Master Control Register */

#define MAST_CTL_MASK           0x0003ef00      /* Reserved bits */
#define MAST_CTL_RTRY_FOREVER   (0 << 28)       /* Max Retries before PCI err*/
#define MAST_CTL_RTRY_DEFAULT   (8 << 28)       /* Max Retries before PCI err*/
#define MAST_CTL_PWON_128       (0 << 24)       /* Posted Write VME Xfer Cnt */
#define MAST_CTL_PWON_256       (1 << 24)       /* Posted Write VME Xfer Cnt */
#define MAST_CTL_PWON_512       (2 << 24)       /* Posted Write VME Xfer Cnt */
#define MAST_CTL_PWON_1024      (3 << 24)       /* Posted Write VME Xfer Cnt */
#define MAST_CTL_PWON_2048      (4 << 24)       /* Posted Write VME Xfer Cnt */
#define MAST_CTL_PWON_4096      (5 << 24)       /* Posted Write VME Xfer Cnt */
#define MAST_CTL_VRL0           (0 << 22)       /* VMEbus Request Level      */
#define MAST_CTL_VRL1           (1 << 22)       /* VMEbus Request Level      */
#define MAST_CTL_VRL2           (2 << 22)       /* VMEbus Request Level      */
#define MAST_CTL_VRL3           (3 << 22)       /* VMEbus Request Level      */
#define MAST_CTL_VRM_FAIR       (1 << 21)       /* FAIR Request Mode         */
#define MAST_CTL_VRM_DEMAND     (0 << 21)       /* Demand Request Mode       */
#define MAST_CTL_VREL_RWD       (0 << 20)       /* Release When Done         */
#define MAST_CTL_VREL_ROR       (1 << 20)       /* Release on Request        */
#define MAST_CTL_VOWN           (1 << 19)       /* Acquire and Hold VMEbus   */
#define MAST_CTL_VOWN_ACK       (1 << 18)       /* VMEbus bus held */
#define MAST_CTL_PABS_32        (0 << 12)       /* 32 Byte PCI Aligned Burst */
#define MAST_CTL_PABS_64        (1 << 12)       /* 64 Byte PCI Aligned Burst */
#define MAST_CTL_PABS_128       (1 << 13)       /* 128 Byte PCI Aligned Burst */
/* Miscellaneous Control Register */

#define MISC_CTL_MASK           0x0820ffff      /* Reserved bits */
#define MISC_CTL_VBTO_DISABLE   (0 << 28)       /*   Forever VMEbus Timeout  */
#define MISC_CTL_VBTO_16USEC    (1 << 28)       /*   16 Usec VMEbus Timeout  */
#define MISC_CTL_VBTO_32USEC    (2 << 28)       /*   32 Usec VMEbus Timeout  */
#define MISC_CTL_VBTO_64USEC    (3 << 28)       /*   64 Usec VMEbus Timeout  */
#define MISC_CTL_VBTO_128USEC   (4 << 28)       /*  128 Usec VMEbus Timeout  */
#define MISC_CTL_VBTO_256USEC   (5 << 28)       /*  256 Usec VMEbus Timeout  */
#define MISC_CTL_VBTO_512USEC   (6 << 28)       /*  512 Usec VMEbus Timeout  */
#define MISC_CTL_VBTO_1024USEC  (7 << 28)       /* 1024 Usec VMEbus Timeout  */
#define MISC_CTL_VARB_PRIORITY  (1 << 26)       /* Priority Arbitration Mode */
#define MISC_CTL_VARB_RROBIN    (0 << 26)       /* Round Robin Arbitration   */
#define MISC_CTL_VARBTO_DISABLE (0 << 24)       /* Round Robin Arbitration   */
#define MISC_CTL_VARBTO_16USEC  (1 << 24)       /* Round Robin Arbitration   */
#define MISC_CTL_VARBTO_256USEC (2 << 24)       /* Round Robin Arbitration   */
#define MISC_CTL_SW_LRST        (1 << 23)       /* Software PCI Reset        */
#define MISC_CTL_SW_SRST        (1 << 22)       /* Software VMEbus Sysreset  */
#define MISC_CTL_BI_MODE        (1 << 20)       /*                           */
#define MISC_CTL_ENGBI          (1 << 19)       /*                           */
#define MISC_CTL_RESCIND        (1 << 18)       /* Rescinding DTACK Enable   */
#define MISC_CTL_NO_RESCIND     (0 << 18)       /* Rescinding DTACK Disable  */
#define MISC_CTL_SYSCON         (1 << 17)       /* Universe is SysController */
#define MISC_CTL_NOT_SYSCON     (0 << 17)       /* Universe not SysController */
#define MISC_CTL_V64AUTO        (1 << 16)       /* Initiate VME64 Auto ID    */

/* Miscellaneous Status Register */

#define MISC_STAT_LCL_SIZE_32   (0 << 30)       /* PCI Bus is 32 bits        */
#define MISC_STAT_LCL_SIZE_64   (1 << 30)       /* PCI Bus is 64 bits        */
#define MISC_STAT_DY4AUTO       (1 << 27)       /* DY4 Auto ID Enable        */
#define MISC_STAT_MYBBSY_NEGATED (1 << 21)      /* Universe Bus Busy Negated */
#define MISC_STAT_DY4DONE       (1 << 19)       /* DY4 Auto ID is Done       */
#define MISC_STAT_TXFE          (1 << 18)       /* Transmit FIFO Empty       */
#define MISC_STAT_RXFE          (1 << 17)       /* Receive FIFO Empty        */

/* VMEbus Slave Image 0 Control */

#define VSI0_CTL_MASK           0x1f08ff3c      /* Reserved Bits */
#define VSI0_CTL_EN             (1 << 31)       /* Image Enable               */
#define VSI0_CTL_PWEN           (1 << 30)       /* Posted Write Enable        */
#define VSI0_CTL_PREN           (1 << 29)       /* Prefetch Read Enable       */
#define VSI0_CTL_AM_DATA        (1 << 22)       /* Respond to Data AM Code    */
#define VSI0_CTL_AM_PGM         (2 << 22)       /* Respond to Prog AM Code    */
#define VSI0_CTL_AM_SUPER       (2 << 20)       /* Respond to Superv AM Code  */
#define VSI0_CTL_AM_USER        (1 << 20)       /* Respond to Non-Priv AM Code*/
#define VSI0_CTL_VAS_A16        (0 << 16)       /* Respond to VME A16         */
#define VSI0_CTL_VAS_A24        (1 << 16)       /* Respond to VME A24         */
#define VSI0_CTL_VAS_A32        (2 << 16)       /* Respond to VME A32         */
#define VSI0_CTL_VAS_USER1      (6 << 16)       /* Respond to VME Space User 1*/
#define VSI0_CTL_VAS_USER2      (7 << 16)       /* Respond to VME Space User 2*/
#define VSI0_CTL_LD64EN         (1 << 7)        /* Enable 64-bit PCI bus Xfer */
#define VSI0_CTL_LLRMW          (1 << 6)        /* Enable PCI lock of VME RMW */
#define VSI0_CTL_LAS_MEM        (0 << 0)        /* PCIbus Memory Space        */
#define VSI0_CTL_LAS_IO         (1 << 0)        /* PCIbus I/O Space           */
#define VSI0_CTL_LAS_CFG        (2 << 0)        /* PCIbus Config Space        */

/* VMEbus Slave Image 0 Base Address Register */

#define VSI0_BS_MASK    0x00000fff

/* VMEbus Slave Image 0 Bound Address Register */

#define VSI0_BD_MASK    0x00000fff

/* VMEbus Slave Image 0 Translation Offset Register */

#define VSI0_TO_MASK    0x00000fff

/* VMEbus Slave Image 1 Control */

#define VSI1_CTL_MASK           0x1f08ff3c      /* Reserved Bits */
#define VSI1_CTL_EN             (1 << 31)       /* Image Enable               */