universe_dy4.h
来自「Curtiss-Wright Controls Embedded Computi」· C头文件 代码 · 共 1,315 行 · 第 1/5 页
H
1,315 行
#define LSI4_CTL_PGM (1 << 14) /* Program AM Code */#define LSI4_CTL_DATA (0 << 14) /* Data AM Code */#define LSI4_CTL_SUP (1 << 12) /* Supervisor AM Code */#define LSI4_CTL_USR (0 << 12) /* User AM Code */#define LSI4_CTL_BLK (1 << 8) /* Supervisor AM Code */#define LSI4_CTL_SINGLE (0 << 8) /* User AM Code */#define LSI4_CTL_PCI_MEM (0 << 0) /* PCI Memory Space */#define LSI4_CTL_PCI_IO (1 << 0) /* PCI I/O Space */#define LSI4_CTL_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space *//* PCI Slave Image Base Address Register 3 */#define LSI4_BS_MASK 0x0000ffff/* PCI Slave Image Bound Address Register 3 */#define LSI4_BD_MASK 0x0000ffff/* PCI Slave Image Translation Offset Register 3 */#define LSI4_TO_MASK 0x0000ffff/* PCI Slave Image Control Register 5 */#define LSI5_CTL_MASK 0x3f380efc /* Mask bits */#define LSI5_CTL_EN (1 << 31) /* Enable PCI Slave Image */#define LSI5_CTL_WP (1 << 30) /* Enable Posted Writes */#define LSI5_CTL_D8 (0 << 22) /* Max VME Data Width = 8 */#define LSI5_CTL_D16 (1 << 22) /* Max VME Data Width = 16 */#define LSI5_CTL_D32 (2 << 22) /* Max VME Data Width = 32 */#define LSI5_CTL_D64 (3 << 22) /* Max VME Data Width = 64 */#define LSI5_CTL_A16 (0 << 16) /* VME Address Space A16 */#define LSI5_CTL_A24 (1 << 16) /* VME Address Space A24 */#define LSI5_CTL_A32 (2 << 16) /* VME Address Space A32 */#define LSI5_CTL_CSR (5 << 16) /* VME Address Space CSR */#define LSI5_CTL_USER1 (6 << 16) /* VME Address Space USER 1 */#define LSI5_CTL_USER2 (7 << 16) /* VME Address Space USER 2 */#define LSI5_CTL_PGM (1 << 14) /* Program AM Code */#define LSI5_CTL_DATA (0 << 14) /* Data AM Code */#define LSI5_CTL_SUP (1 << 12) /* Supervisor AM Code */#define LSI5_CTL_USR (0 << 12) /* User AM Code */#define LSI5_CTL_BLK (1 << 8) /* Supervisor AM Code */#define LSI5_CTL_SINGLE (0 << 8) /* User AM Code */#define LSI5_CTL_PCI_MEM (0 << 0) /* PCI Memory Space */#define LSI5_CTL_PCI_IO (1 << 0) /* PCI I/O Space */#define LSI5_CTL_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space *//* PCI Slave Image Base Address Register 3 */#define LSI5_BS_MASK 0x0000ffff/* PCI Slave Image Bound Address Register 3 */#define LSI5_BD_MASK 0x0000ffff/* PCI Slave Image Translation Offset Register 3 */#define LSI5_TO_MASK 0x0000ffff/* PCI Slave Image Control Register 6 */#define LSI6_CTL_MASK 0x3f380efc /* Mask bits */#define LSI6_CTL_EN (1 << 31) /* Enable PCI Slave Image */#define LSI6_CTL_WP (1 << 30) /* Enable Posted Writes */#define LSI6_CTL_D8 (0 << 22) /* Max VME Data Width = 8 */#define LSI6_CTL_D16 (1 << 22) /* Max VME Data Width = 16 */#define LSI6_CTL_D32 (2 << 22) /* Max VME Data Width = 32 */#define LSI6_CTL_D64 (3 << 22) /* Max VME Data Width = 64 */#define LSI6_CTL_A16 (0 << 16) /* VME Address Space A16 */#define LSI6_CTL_A24 (1 << 16) /* VME Address Space A24 */#define LSI6_CTL_A32 (2 << 16) /* VME Address Space A32 */#define LSI6_CTL_CSR (5 << 16) /* VME Address Space CSR */#define LSI6_CTL_USER1 (6 << 16) /* VME Address Space USER 1 */#define LSI6_CTL_USER2 (7 << 16) /* VME Address Space USER 2 */#define LSI6_CTL_PGM (1 << 14) /* Program AM Code */#define LSI6_CTL_DATA (0 << 14) /* Data AM Code */#define LSI6_CTL_SUP (1 << 12) /* Supervisor AM Code */#define LSI6_CTL_USR (0 << 12) /* User AM Code */#define LSI6_CTL_BLK (1 << 8) /* Supervisor AM Code */#define LSI6_CTL_SINGLE (0 << 8) /* User AM Code */#define LSI6_CTL_PCI_MEM (0 << 0) /* PCI Memory Space */#define LSI6_CTL_PCI_IO (1 << 0) /* PCI I/O Space */#define LSI6_CTL_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space *//* PCI Slave Image Base Address Register 3 */#define LSI6_BS_MASK 0x0000ffff/* PCI Slave Image Bound Address Register 3 */#define LSI6_BD_MASK 0x0000ffff/* PCI Slave Image Translation Offset Register 3 */#define LSI6_TO_MASK 0x0000ffff/* PCI Slave Image Control Register 7 */#define LSI7_CTL_MASK 0x3f380efc /* Mask bits */#define LSI7_CTL_EN (1 << 31) /* Enable PCI Slave Image */#define LSI7_CTL_WP (1 << 30) /* Enable Posted Writes */#define LSI7_CTL_D8 (0 << 22) /* Max VME Data Width = 8 */#define LSI7_CTL_D16 (1 << 22) /* Max VME Data Width = 16 */#define LSI7_CTL_D32 (2 << 22) /* Max VME Data Width = 32 */#define LSI7_CTL_D64 (3 << 22) /* Max VME Data Width = 64 */#define LSI7_CTL_A16 (0 << 16) /* VME Address Space A16 */#define LSI7_CTL_A24 (1 << 16) /* VME Address Space A24 */#define LSI7_CTL_A32 (2 << 16) /* VME Address Space A32 */#define LSI7_CTL_CSR (5 << 16) /* VME Address Space CSR */#define LSI7_CTL_USER1 (6 << 16) /* VME Address Space USER 1 */#define LSI7_CTL_USER2 (7 << 16) /* VME Address Space USER 2 */#define LSI7_CTL_PGM (1 << 14) /* Program AM Code */#define LSI7_CTL_DATA (0 << 14) /* Data AM Code */#define LSI7_CTL_SUP (1 << 12) /* Supervisor AM Code */#define LSI7_CTL_USR (0 << 12) /* User AM Code */#define LSI7_CTL_BLK (1 << 8) /* Supervisor AM Code */#define LSI7_CTL_SINGLE (0 << 8) /* User AM Code */#define LSI7_CTL_PCI_MEM (0 << 0) /* PCI Memory Space */#define LSI7_CTL_PCI_IO (1 << 0) /* PCI I/O Space */#define LSI7_CTL_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space *//* PCI Slave Image Base Address Register 3 */#define LSI7_BS_MASK 0x0000ffff/* PCI Slave Image Bound Address Register 3 */#define LSI7_BD_MASK 0x0000ffff/* PCI Slave Image Translation Offset Register 3 */#define LSI7_TO_MASK 0x0000ffff/* PCI Special Cycle Control Register */#define SCYC_CTL_MASK 0xfffffffc#define SCYC_CTL_DISABLE (0) /* Disable Special Cycle Gen */#define SCYC_CTL_RMW (1) /* RMW Special Cycle */#define SCYC_CTL_ADO (2) /* ADO Special Cycle *//* PCI Special Cycle Address Register */#define SCYC_ADDR_MASK 0x3/* PCI Miscellaneous Register */#define LMISC_CRT_INFINITE (0 << 28) /* Coupled Request Timeout */#define LMISC_CRT_128_USEC (1 << 28) /* Coupled Request Timeout */#define LMISC_CRT_256_USEC (2 << 28) /* Coupled Request Timeout */#define LMISC_CRT_512_USEC (3 << 28) /* Coupled Request Timeout */#define LMISC_CRT_1024_USEC (4 << 28) /* Coupled Request Timeout */#define LMISC_CRT_2048_USEC (5 << 28) /* Coupled Request Timeout */#define LMISC_CRT_4096_USEC (6 << 28) /* Coupled Request Timeout */#define LMISC_CWT_DISABLE (0 << 24) /* Coupled Window Timeout */ /* Immediate Release after first transaction */#define LMISC_CWT_16_CLKS (1 << 24) /* Coupled Window Timeout */#define LMISC_CWT_32_CLKS (2 << 24) /* Coupled Window Timeout */#define LMISC_CWT_64_CLKS (3 << 24) /* Coupled Window Timeout */#define LMISC_CWT_128_CLKS (4 << 24) /* Coupled Window Timeout */#define LMISC_CWT_256_CLKS (5 << 24) /* Coupled Window Timeout */#define LMISC_CWT_512_CLKS (6 << 24) /* Coupled Window Timeout *//* * Special PCI Slave Image * - provides access to all of A16 and most of A24 VME Space */#define SLSI_EN (1 << 31) /* Enable PCI Slave Image */#define SLSI_WP (1 << 30) /* Enable Posted Writes */#define SLSI_D16_0 (0 << 20) /* Special image 0 Max VME Data Width = 16 */#define SLSI_D32_0 (1 << 20) /* Special image 0 Max VME Data Width = 32 */#define SLSI_D16_1 (0 << 21) /* Special image 1 Max VME Data Width = 16 */#define SLSI_D32_1 (1 << 21) /* Special image 1 Max VME Data Width = 32 */#define SLSI_D16_2 (0 << 22) /* Special image 2 Max VME Data Width = 16 */#define SLSI_D32_2 (1 << 22) /* Special image 2 Max VME Data Width = 32 */#define SLSI_D16_3 (0 << 23) /* Special image 3 Max VME Data Width = 16 */#define SLSI_D32_3 (1 << 23) /* Special image 3 Max VME Data Width = 32 */#define SLSI_DATA_0 (0 << 12) /* Special image 0 Data AM Code */#define SLSI_PGM_0 (1 << 12) /* Special image 0 Program AM Code */#define SLSI_DATA_1 (0 << 13) /* Special image 1 Data AM Code */#define SLSI_PGM_1 (1 << 13) /* Special image 1 Program AM Code */#define SLSI_DATA_2 (0 << 14) /* Special image 2 Data AM Code */#define SLSI_PGM_2 (1 << 14) /* Special image 2 Program AM Code */#define SLSI_DATA_3 (0 << 15) /* Special image 3 Data AM Code */#define SLSI_PGM_3 (1 << 15) /* Special image 3 Program AM Code */#define SLSI_USR_0 (0 << 8) /* Special image 0 User AM Code */#define SLSI_SUP_0 (1 << 8) /* Special image 0 Supervisor AM Code */#define SLSI_USR_1 (0 << 9) /* Special image 1 User AM Code */#define SLSI_SUP_1 (1 << 9) /* Special image 1 Supervisor AM Code */#define SLSI_USR_2 (0 << 10) /* Special image 2 User AM Code */#define SLSI_SUP_2 (1 << 10) /* Special image 2 Supervisor AM Code */#define SLSI_USR_3 (0 << 11) /* Special image 3 User AM Code */#define SLSI_SUP_3 (1 << 11) /* Special image 3 Supervisor AM Code */#define SLSI_PCI_MEM (0 << 0) /* PCI Memory Space */#define SLSI_PCI_IO (1 << 0) /* PCI I/O Space */#define SLSI_PCI_CONFIG (2 << 0) /* PCI Type 1 Config Space */#define SLSI_BS_MASK (0x000000FC) /* Base address mask *//* Special slave image regons masks. */#define SLSI_REGN0_MASK 0x1#define SLSI_REGN1_MASK 0x2 #define SLSI_REGN2_MASK 0x4#define SLSI_REGN3_MASK 0x8#define SLSI_VDW_16 0x0#define SLSI_VDW_32 0xF#define SLSI_PGM_DAT 0x0#define SLSI_PGM_PRG 0xF#define SLSI_SUPER_USR 0x0#define SLSI_SUPER_SUP 0xF/* PCI Command Error Log Register */#define L_CMDERR_LOG (0xf << 28) /* Command Error Log */#define L_CMDERR_MASK 0x078fffff /* Reserved bits */#define L_CMDERR_M_ERR (1 << 27) /* Multiple Error Occurred */#define L_CMDERR_L_STAT (1 << 23) /* Logs are valid and halted */#define L_CMDERR_L_ENABLE (1 << 23) /* Clear and Enable Logging *//* DMA Transfer Control Register */#define DCTL_MASK 0x7f380e7f /* Reserved bits */#define DCTL_L2V (1 << 31) /* PCI-to-VME transfer */#define DCTL_VDW_8 (0) /* Maximum data width 8 bits */#define DCTL_VDW_16 (1 << 22) /* Maximum data width 16 bits */#define DCTL_VDW_32 (2 << 22) /* Maximum data width 32 bits */#define DCTL_VDW_64 (3 << 22) /* Maximum data width 64 bits */#define DCTL_VAS_A16 (0) /* VME address space A16 */#define DCTL_VAS_A24 (1 << 16) /* VME address space A24 */#define DCTL_VAS_A32 (2 << 16) /* VME address space A32 */#define DCTL_VAS_USER1 (6 << 16) /* VME address space User1 */#define DCTL_VAS_USER2 (7 << 16) /* VME address space User2 */#define DCTL_PGM_DATA (0) /* Data AM code */#define DCTL_PGM_PRGM (1 << 14) /* Program AM code */#define DCTL_SUPER_USER (0) /* Non-privileged AM code */#define DCTL_SUPER_SUP (1 << 12) /* Supervisor AM code */#define DCTL_VCT_EN (1 << 8) /* Block mode capable */#define DCTL_LD64EN (1 << 7) /* 64-bit PCI transactions *//* DMA Transfer Byte Count Register */#define DTBC_MASK 0xff000000/* DMA General Control/Status Register */#define DGCS_MASK 0x00000000 /* Reserved bits */#define DGCS_GO (1 << 31) /* Start DMA */#define DGCS_STOP_REQ (1 << 30) /* Stop Request */#define DGCS_HALT_REQ (1 << 29) /* Halt Request */#define DGCS_CHAIN (1 << 27) /* DMA chaining */#define DGCS_VON_DONE (0) /* Transfer count until done*/#define DGCS_VON_256 (1 << 20) /* Transfer count 256 bytes */⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?