top.stp

来自「sdram 控制器的verilog 实现」· STP 代码 · 共 629 行 · 第 1/5 页

          </bus>
          <net is_signal_inverted="no" name="user_interface:inst3|r_data_valid"/>
          <bus is_signal_inverted="no" link="all" name="user_interface:inst3|ram_addr" order="lsb_to_msb" radix="unsigned_dec" state="collapse" type="register">
            <net is_signal_inverted="no" name="user_interface:inst3|ram_addr[0]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|ram_addr[1]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|ram_addr[2]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|ram_addr[3]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|ram_addr[4]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|ram_addr[5]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|ram_addr[6]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|ram_addr[7]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|ram_addr[8]"/>
          </bus>
          <net is_signal_inverted="no" name="user_interface:inst3|read_ack"/>
          <net is_signal_inverted="no" name="user_interface:inst3|read_req"/>
          <bus is_signal_inverted="no" link="all" name="user_interface:inst3|rom_addr" order="lsb_to_msb" radix="unsigned_dec" state="collapse" type="register">
            <net is_signal_inverted="no" name="user_interface:inst3|rom_addr[0]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|rom_addr[1]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|rom_addr[2]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|rom_addr[3]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|rom_addr[4]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|rom_addr[5]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|rom_addr[6]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|rom_addr[7]"/>
          </bus>
          <net is_signal_inverted="no" name="user_interface:inst3|setup_done"/>
          <bus is_signal_inverted="no" link="all" name="user_interface:inst3|sys_addr" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[0]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[1]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[2]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[3]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[4]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[5]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[6]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[7]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[8]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[9]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[10]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[11]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[12]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[13]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[14]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[15]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[16]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[17]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[18]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[19]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[20]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|sys_addr[21]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="user_state" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="user_interface:inst3|user_state.gen_read_req"/>
            <net is_signal_inverted="no" name="user_interface:inst3|user_state.gen_write_req"/>
            <net is_signal_inverted="no" name="user_interface:inst3|user_state.idle"/>
            <net is_signal_inverted="no" name="user_interface:inst3|user_state.wait_read_ack"/>
            <net is_signal_inverted="no" name="user_interface:inst3|user_state.wait_setup"/>
            <net is_signal_inverted="no" name="user_interface:inst3|user_state.wait_write_ack"/>
          </bus>
          <net is_signal_inverted="no" name="user_interface:inst3|w_data_valid"/>
          <net is_signal_inverted="no" name="user_interface:inst3|write_ack"/>
          <net is_signal_inverted="no" name="user_interface:inst3|write_req"/>
          <bus is_signal_inverted="no" link="all" name="sdram_top:inst|main_fsm:U0|c_state" order="lsb_to_msb" radix="unsigned_dec" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|c_state[0]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|c_state[1]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|c_state[2]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|c_state[3]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sdram_top:inst|main_fsm:U0|clk_m_cnt" order="lsb_to_msb" radix="unsigned_dec" state="collapse" type="register">
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|clk_m_cnt[0]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|clk_m_cnt[1]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|clk_m_cnt[2]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|clk_m_cnt[3]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|clk_m_cnt[4]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|clk_m_cnt[5]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|clk_m_cnt[6]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|clk_m_cnt[7]"/>
            <net is_signal_inverted="no" name="sdram_top:inst|main_fsm:U0|clk_m_cnt[8]"/>
          </bus>
        </data_view>
        <setup_view>
          <net is_signal_inverted="no" name="sdram_cke"/>
          <net is_signal_inverted="no" name="sdram_cs_n"/>
          <net is_signal_inverted="no" name="sdram_ras_n"/>
          <net is_signal_inverted="no" name="sdram_cas_n"/>
          <net is_signal_inverted="no" name="sdram_we_n"/>
          <bus is_signal_inverted="no" link="all" name="sdram_ba[1..0]" order="msb_to_lsb" radix="bin" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="sdram_ba[0]"/>
            <net is_signal_inverted="no" name="sdram_ba[1]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sdram_addr[0..11]" order="lsb_to_msb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="sdram_addr[0]"/>
            <net is_signal_inverted="no" name="sdram_addr[1]"/>
            <net is_signal_inverted="no" name="sdram_addr[2]"/>
            <net is_signal_inverted="no" name="sdram_addr[3]"/>
            <net is_signal_inverted="no" name="sdram_addr[4]"/>
            <net is_signal_inverted="no" name="sdram_addr[5]"/>
            <net is_signal_inverted="no" name="sdram_addr[6]"/>
            <net is_signal_inverted="no" name="sdram_addr[7]"/>
            <net is_signal_inverted="no" name="sdram_addr[8]"/>
            <net is_signal_inverted="no" name="sdram_addr[9]"/>
            <net is_signal_inverted="no" name="sdram_addr[10]"/>
            <net is_signal_inverted="no" name="sdram_addr[11]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sdram_data[0..15]" order="lsb_to_msb" radix="hex" state="collapse" type="bidir pin">
            <net is_signal_inverted="no" name="sdram_data[0]"/>
            <net is_signal_inverted="no" name="sdram_data[1]"/>
            <net is_signal_inverted="no" name="sdram_data[2]"/>
            <net is_signal_inverted="no" name="sdram_data[3]"/>
            <net is_signal_inverted="no" name="sdram_data[4]"/>
            <net is_signal_inverted="no" name="sdram_data[5]"/>
            <net is_signal_inverted="no" name="sdram_data[6]"/>
            <net is_signal_inverted="no" name="sdram_data[7]"/>
            <net is_signal_inverted="no" name="sdram_data[8]"/>
            <net is_signal_inverted="no" name="sdram_data[9]"/>
            <net is_signal_inverted="no" name="sdram_data[10]"/>
            <net is_signal_inverted="no" name="sdram_data[11]"/>
            <net is_signal_inverted="no" name="sdram_data[12]"/>
            <net is_signal_inverted="no" name="sdram_data[13]"/>
            <net is_signal_inverted="no" name="sdram_data[14]"/>
            <net is_signal_inverted="no" name="sdram_data[15]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sdram_dqm[1..0]" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="sdram_dqm[0]"/>
            <net is_signal_inverted="no" name="sdram_dqm[1]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="user_interface:inst3|ram_addr" order="lsb_to_msb" radix="unsigned_dec" state="collapse" type="register">