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sdram 控制器的verilog 实现

          <wire name="user_interface:inst3|read_ack" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|read_req" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|rom_addr[0]" tap_mode="classic" type="register"/>
          <wire name="user_interface:inst3|rom_addr[1]" tap_mode="classic" type="register"/>
          <wire name="user_interface:inst3|rom_addr[2]" tap_mode="classic" type="register"/>
          <wire name="user_interface:inst3|rom_addr[3]" tap_mode="classic" type="register"/>
          <wire name="user_interface:inst3|rom_addr[4]" tap_mode="classic" type="register"/>
          <wire name="user_interface:inst3|rom_addr[5]" tap_mode="classic" type="register"/>
          <wire name="user_interface:inst3|rom_addr[6]" tap_mode="classic" type="register"/>
          <wire name="user_interface:inst3|rom_addr[7]" tap_mode="classic" type="register"/>
          <wire name="user_interface:inst3|setup_done" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[0]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[10]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[11]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[12]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[13]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[14]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[15]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[16]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[17]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[18]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[19]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[1]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[20]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[21]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[2]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[3]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[4]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[5]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[6]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[7]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[8]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|sys_addr[9]" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|user_state.gen_read_req" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|user_state.gen_write_req" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|user_state.idle" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|user_state.wait_read_ack" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|user_state.wait_setup" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|user_state.wait_write_ack" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|w_data_valid" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|write_ack" tap_mode="classic" type="combinatorial"/>
          <wire name="user_interface:inst3|write_req" tap_mode="classic" type="combinatorial"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <net is_signal_inverted="no" name="sdram_cke"/>
          <net is_signal_inverted="no" name="sdram_cs_n"/>
          <net is_signal_inverted="no" name="sdram_ras_n"/>
          <net is_signal_inverted="no" name="sdram_cas_n"/>
          <net is_signal_inverted="no" name="sdram_we_n"/>
          <bus is_signal_inverted="no" link="all" name="sdram_ba[1..0]" order="msb_to_lsb" radix="bin" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="sdram_ba[0]"/>
            <net is_signal_inverted="no" name="sdram_ba[1]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sdram_addr[0..11]" order="lsb_to_msb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="sdram_addr[0]"/>
            <net is_signal_inverted="no" name="sdram_addr[1]"/>
            <net is_signal_inverted="no" name="sdram_addr[2]"/>
            <net is_signal_inverted="no" name="sdram_addr[3]"/>
            <net is_signal_inverted="no" name="sdram_addr[4]"/>
            <net is_signal_inverted="no" name="sdram_addr[5]"/>
            <net is_signal_inverted="no" name="sdram_addr[6]"/>
            <net is_signal_inverted="no" name="sdram_addr[7]"/>
            <net is_signal_inverted="no" name="sdram_addr[8]"/>
            <net is_signal_inverted="no" name="sdram_addr[9]"/>
            <net is_signal_inverted="no" name="sdram_addr[10]"/>
            <net is_signal_inverted="no" name="sdram_addr[11]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sdram_data[0..15]" order="lsb_to_msb" radix="hex" state="collapse" type="bidir pin">
            <net is_signal_inverted="no" name="sdram_data[0]"/>
            <net is_signal_inverted="no" name="sdram_data[1]"/>
            <net is_signal_inverted="no" name="sdram_data[2]"/>
            <net is_signal_inverted="no" name="sdram_data[3]"/>
            <net is_signal_inverted="no" name="sdram_data[4]"/>
            <net is_signal_inverted="no" name="sdram_data[5]"/>
            <net is_signal_inverted="no" name="sdram_data[6]"/>
            <net is_signal_inverted="no" name="sdram_data[7]"/>
            <net is_signal_inverted="no" name="sdram_data[8]"/>
            <net is_signal_inverted="no" name="sdram_data[9]"/>
            <net is_signal_inverted="no" name="sdram_data[10]"/>
            <net is_signal_inverted="no" name="sdram_data[11]"/>
            <net is_signal_inverted="no" name="sdram_data[12]"/>
            <net is_signal_inverted="no" name="sdram_data[13]"/>
            <net is_signal_inverted="no" name="sdram_data[14]"/>
            <net is_signal_inverted="no" name="sdram_data[15]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sdram_dqm[1..0]" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="sdram_dqm[0]"/>
            <net is_signal_inverted="no" name="sdram_dqm[1]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="user_interface:inst3|data_from_sdram" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[0]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[1]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[2]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[3]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[4]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[5]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[6]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[7]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[8]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[9]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[10]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[11]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[12]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[13]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[14]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_from_sdram[15]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="user_interface:inst3|data_to_sdram" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[0]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[1]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[2]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[3]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[4]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[5]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[6]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[7]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[8]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[9]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[10]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[11]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[12]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[13]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[14]"/>
            <net is_signal_inverted="no" name="user_interface:inst3|data_to_sdram[15]"/>