top.tan.rpt

sdram 控制器的verilog 实现

; Type                                                      ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                               ; To                                                                                           ; From Clock                                 ; To Clock                                   ; Failed Paths ;
+-----------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Worst-case tsu                                            ; N/A       ; None                             ; 13.464 ns                        ; key_rst_n                                                                                                                                                          ; sdram_top:inst|refresh:U2|refresh_cnt[3]                                                     ; --                                         ; clk                                        ; 0            ;
; Worst-case tco                                            ; N/A       ; None                             ; 11.287 ns                        ; user_interface:inst3|rom256:rom256_inst|altsyncram:altsyncram_component|altsyncram_2361:auto_generated|altsyncram_fk72:altsyncram1|ram_block3a0~porta_address_reg7 ; sdram_data[11]                                                                               ; clk                                        ; --                                         ; 0            ;
; Worst-case tpd                                            ; N/A       ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                           ; altera_reserved_tdo                                                                          ; --                                         ; --                                         ; 0            ;
; Worst-case th                                             ; N/A       ; None                             ; 3.790 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                                                       ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0]                    ; --                                         ; altera_internal_jtag~TCKUTAP               ; 0            ;
; Clock Setup: 'pll_50:inst1|altpll:altpll_component|_clk0' ; 1.195 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[1]                                                                       ; sdram_top:inst|refresh:U2|refresh_cnt[3]                                                     ; clk                                        ; pll_50:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'clk'                                        ; 45.930 ns ; 20.00 MHz ( period = 50.000 ns ) ; 245.70 MHz ( period = 4.070 ns ) ; reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[1]                                                                       ; reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[1] ; clk                                        ; clk                                        ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'               ; N/A       ; None                             ; 64.09 MHz ( period = 15.604 ns ) ; user_interface:inst3|ram512:ram512_inst|altsyncram:altsyncram_component|altsyncram_0qe1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]               ; sld_hub:sld_hub_inst|hub_tdo_reg                                                             ; altera_internal_jtag~TCKUTAP               ; altera_internal_jtag~TCKUTAP               ; 0            ;
; Clock Hold: 'pll_50:inst1|altpll:altpll_component|_clk0'  ; 0.822 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; user_interface:inst3|read_req                                                                                                                                      ; user_interface:inst3|read_req                                                                ; pll_50:inst1|altpll:altpll_component|_clk0 ; pll_50:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'clk'                                         ; 1.323 ns  ; 20.00 MHz ( period = 50.000 ns ) ; N/A                              ; reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[4]                                                                       ; reset:inst2|counter:inst|lpm_counter:lpm_counter_component|cntr_vui:auto_generated|safe_q[4] ; clk                                        ; clk                                        ; 0            ;
; Total number of failed paths                              ;           ;                                  ;                                  ;                                                                                                                                                                    ;                                                                                              ;                                            ;                                            ; 0            ;
+-----------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; On                 ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                               ;
+-----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+----------+--------------+
; Clock Node Name                               ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset   ; Phase offset ;