top.v

sdram 控制器的verilog 实现

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module top(
	clk,
	rst_n,
	sdram_cke,
	sdram_cs_n,
	sdram_ras_n,
	sdram_cas_n,
	sdram_we_n,
	sdram_addr,
	sdram_ba,
	sdram_data,
	sdram_dqm
);

input	clk;
input	rst_n;
output	sdram_cke;
output	sdram_cs_n;
output	sdram_ras_n;
output	sdram_cas_n;
output	sdram_we_n;
output	[11:0] sdram_addr;
output	[1:0] sdram_ba;
inout	[15:0] sdram_data;
output	[1:0] sdram_dqm;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	[8:0] SYNTHESIZED_WIRE_2;
wire	[15:0] SYNTHESIZED_WIRE_3;
wire	[21:0] SYNTHESIZED_WIRE_4;
wire	SYNTHESIZED_WIRE_5;
wire	SYNTHESIZED_WIRE_6;
wire	SYNTHESIZED_WIRE_7;
wire	SYNTHESIZED_WIRE_8;
wire	SYNTHESIZED_WIRE_9;
wire	[15:0] SYNTHESIZED_WIRE_10;





sdram_top	b2v_inst(.clk(clk),
.rst_n(rst_n),.read_req(SYNTHESIZED_WIRE_0),.write_req(SYNTHESIZED_WIRE_1),.burst_len(SYNTHESIZED_WIRE_2),.data_from_sys(SYNTHESIZED_WIRE_3),.sdr_DATA(sdram_data),.sys_addr(SYNTHESIZED_WIRE_4),.read_ack(SYNTHESIZED_WIRE_5),.write_ack(SYNTHESIZED_WIRE_6),.r_data_valid(SYNTHESIZED_WIRE_7),.w_data_valid(SYNTHESIZED_WIRE_8),.setup_done(SYNTHESIZED_WIRE_9),.sdr_CKE(sdram_cke),.sdr_CSn(sdram_cs_n),.sdr_RASn(sdram_ras_n),.sdr_CASn(sdram_cas_n),.sdr_WEn(sdram_we_n),.data_to_sys(SYNTHESIZED_WIRE_10),.sdr_ADDR(sdram_addr),.sdr_BA(sdram_ba),.sdr_DMQ(sdram_dqm));

user_interface	b2v_inst3(.clk(clk),
.rst_n(rst_n),.read_ack(SYNTHESIZED_WIRE_5),.write_ack(SYNTHESIZED_WIRE_6),.r_data_valid(SYNTHESIZED_WIRE_7),.w_data_valid(SYNTHESIZED_WIRE_8),.setup_done(SYNTHESIZED_WIRE_9),.data_from_sdram(SYNTHESIZED_WIRE_10),.read_req(SYNTHESIZED_WIRE_0),.write_req(SYNTHESIZED_WIRE_1),.burst_len(SYNTHESIZED_WIRE_2),.data_to_sdram(SYNTHESIZED_WIRE_3),.sys_addr(SYNTHESIZED_WIRE_4));
defparam	b2v_inst3.gen_read_req = 'b001000;
defparam	b2v_inst3.gen_write_req = 'b000010;
defparam	b2v_inst3.idle = 'b100000;
defparam	b2v_inst3.Tp = 3;
defparam	b2v_inst3.wait_read_ack = 'b010000;
defparam	b2v_inst3.wait_setup = 'b000001;
defparam	b2v_inst3.wait_write_ack = 'b000100;


endmodule