top.qsf

sdram 控制器的verilog 实现

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:59:40  SEPTEMBER 14, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name EDA_TEST_BENCH_NAME testbench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME top_inst -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/testbench.v -section_id testbench
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT testbench/singal.do -section_id eda_simulation
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_instance_assignment -name GLOBAL_SIGNAL ON -to "sdram_top:inst|init_fsm:U1|init_done"
set_location_assignment PIN_6 -to sdram_addr[0]
set_location_assignment PIN_5 -to sdram_addr[1]
set_location_assignment PIN_4 -to sdram_addr[2]
set_location_assignment PIN_3 -to sdram_addr[3]
set_location_assignment PIN_60 -to sdram_addr[4]
set_location_assignment PIN_59 -to sdram_addr[5]
set_location_assignment PIN_58 -to sdram_addr[6]
set_location_assignment PIN_57 -to sdram_addr[7]
set_location_assignment PIN_56 -to sdram_addr[8]
set_location_assignment PIN_55 -to sdram_addr[9]
set_location_assignment PIN_7 -to sdram_addr[10]
set_location_assignment PIN_54 -to sdram_addr[11]
set_location_assignment PIN_11 -to sdram_ba[0]
set_location_assignment PIN_8 -to sdram_ba[1]
set_location_assignment PIN_14 -to sdram_cas_n
set_location_assignment PIN_53 -to sdram_cke
set_location_assignment PIN_38 -to sdram_clk
set_location_assignment PIN_12 -to sdram_cs_n
set_location_assignment PIN_41 -to sdram_data[0]
set_location_assignment PIN_39 -to sdram_data[1]
set_location_assignment PIN_23 -to sdram_data[2]
set_location_assignment PIN_21 -to sdram_data[3]
set_location_assignment PIN_20 -to sdram_data[4]
set_location_assignment PIN_19 -to sdram_data[5]
set_location_assignment PIN_18 -to sdram_data[6]
set_location_assignment PIN_17 -to sdram_data[7]
set_location_assignment PIN_49 -to sdram_data[8]
set_location_assignment PIN_48 -to sdram_data[9]
set_location_assignment PIN_47 -to sdram_data[10]
set_location_assignment PIN_46 -to sdram_data[11]
set_location_assignment PIN_45 -to sdram_data[12]
set_location_assignment PIN_44 -to sdram_data[13]
set_location_assignment PIN_43 -to sdram_data[14]
set_location_assignment PIN_42 -to sdram_data[15]
set_location_assignment PIN_16 -to sdram_dqm[0]
set_location_assignment PIN_50 -to sdram_dqm[1]
set_location_assignment PIN_13 -to sdram_ras_n
set_location_assignment PIN_15 -to sdram_we_n
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[0]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[1]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[2]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[3]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[4]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[5]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[6]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[7]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[8]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[9]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[10]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_addr[11]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_ba[0]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_ba[1]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_cas_n
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_cke
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_clk
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_cs_n
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[0]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[1]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[2]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[3]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[4]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[5]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[6]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[7]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[8]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[9]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[10]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[11]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[12]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[13]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[14]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_data[15]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_dqm[0]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_dqm[1]
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_ras_n
set_instance_assignment -name IO_STANDARD LVTTL -to sdram_we_n
set_location_assignment PIN_28 -to clk
set_location_assignment PIN_2 -to reset_n
set_location_assignment PIN_180 -to key_rst_n
set_instance_assignment -name IO_STANDARD LVTTL -to clk
set_instance_assignment -name IO_STANDARD LVTTL -to reset_n
set_instance_assignment -name IO_STANDARD LVTTL -to key_rst_n
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE top.stp
set_global_assignment -name VERILOG_FILE pll/pll_50.v
set_global_assignment -name VERILOG_FILE delay_reset/counter.v
set_global_assignment -name BDF_FILE delay_reset/reset.bdf
set_global_assignment -name BDF_FILE top.bdf
set_global_assignment -name COMMAND_MACRO_FILE testbench/singal.do
set_global_assignment -name VERILOG_FILE testbench/testbench.v
set_global_assignment -name BSF_FILE source_user/ram512.bsf
set_global_assignment -name MIF_FILE source_user/ram512.mif
set_global_assignment -name VERILOG_FILE source_user/ram512.v
set_global_assignment -name BSF_FILE source_user/rom256.bsf
set_global_assignment -name VERILOG_FILE source_user/rom256.v
set_global_assignment -name MIF_FILE source_user/rom_value.mif
set_global_assignment -name BSF_FILE source_user/user_interface.bsf
set_global_assignment -name VERILOG_FILE source_user/user_interface.v
set_global_assignment -name VERILOG_FILE source_sdram/init_fsm.v
set_global_assignment -name VERILOG_FILE source_sdram/main_fsm.v
set_global_assignment -name VERILOG_FILE source_sdram/refresh.v
set_global_assignment -name VERILOG_FILE source_sdram/sdr_par.v
set_global_assignment -name VERILOG_FILE source_sdram/sdr_sig.v
set_global_assignment -name BSF_FILE source_sdram/sdram_top.bsf
set_global_assignment -name VERILOG_FILE source_sdram/sdram_top.v
set_global_assignment -name HEX_FILE source_user/rom_value.hex
set_global_assignment -name HEX_FILE source_user/ram512.hex
set_global_assignment -name SIGNALTAP_FILE top.stp