user_interface.v

sdram 控制器的verilog 实现

/*
这个模块是用户用于测试sdram controller的,主要思路如下:(读取rom数据，写入sdram,然后在读取sdram数据写入ram)
①先等待setup_done信号的到来,此外还加了个计数器time_cnt,用于延时10s,主要目的为了有足够时间让signalTAP抓取信号
②对sdram进行写,先产生写请求信号，并同时提供sdram地址和burst_len的长达
③接着当w_data_valid信号有效,改变rom地址 (详细请见自己画的时序图)
④对sdram产生读请求信号,并同时提供sdram地址和burst_len的长达
⑤接着当r_data_valid信号有效,改变ram地址 (详细请见自己画的时序图)
*/
`timescale 1ns/100ps
module user_interface(
						//input
						clk,
						rst_n,
						//input from sdram controler
						read_ack,
						write_ack,
						r_data_valid,
						w_data_valid,
						data_from_sdram,
						setup_done,
						
						//output to sdram controller
						read_req,
						write_req,
						burst_len,
						sys_addr,
						data_to_sdram
						//output to rom
						);
//------------------------io-------------------------						
input 			clk;
input 			rst_n;
input 			read_ack;
input			write_ack;
input 			r_data_valid;
input			w_data_valid;
input[15:0]		data_from_sdram;
input 			setup_done;



output reg			read_req;
output reg  		write_req;
output reg[8:0]		burst_len;
output reg[21:0]	sys_addr;

output[15:0]		data_to_sdram;

//-------------------paramter---------------------
parameter 	wait_setup	=6'b000001,
		gen_write_req	=6'b000010,
		wait_write_ack	=6'b000100,
		gen_read_req	=6'b001000,
		wait_read_ack	=6'b010000,
		idle			=6'b100000;	
parameter Tp=3;
//-------------------variable---------------------

//rom signal
reg[7:0]		rom_addr;
//ram singal
reg[8:0]		ram_addr;
reg				wren;
//state varibale
reg[5:0]		user_state;

//for test 
reg[28:0]       time_cnt;
//---------------instantiation--------------------

rom256	rom256_inst (
	.address ( rom_addr ),
	.clock ( clk ),
	.q (data_to_sdram)
	);

ram512	ram512_inst (
	.address ( ram_addr ),
	.clock ( clk ),
	.data ( data_from_sdram ),
	.wren ( wren ),
	.q ()
	);

//-----------------------------main code---------------------------------
always@(posedge clk)
	begin
		if(!rst_n)
			begin
				read_req	<=	#Tp	1'b0;
				write_req	<=	#Tp	1'b0;
				burst_len	<=	#Tp	9'd0;
				sys_addr	<=	#Tp	22'h000000;
				
				wren		<=	#Tp 1'b1;	//only permit to write ram
				ram_addr	<=	#Tp	9'd0;
				rom_addr	<=	#Tp	8'd0;
				
				user_state	<=	#Tp	wait_setup;
				
				time_cnt	<=	#Tp 29'd0;
			end
		else
			begin
				case(user_state)
					wait_setup:
						begin
						//delay for user can catch the signal 
							time_cnt	<=	#Tp time_cnt+1'b1;
							if(setup_done && (time_cnt==29'd500000000))
								begin
									user_state	<=	#Tp	gen_write_req;
								end
						end
					gen_write_req:
						begin
							burst_len	<=	#Tp	9'd255;		//write 8 word to sdram
							sys_addr	<=	#Tp	22'h00000f;	//from addr at 0xf
							write_req	<=	#Tp	1'b1;
							rom_addr	<=	#Tp	8'd0;
							user_state	<=	#Tp	wait_write_ack;						
						end					
					wait_write_ack:
						begin
							if(write_ack)
								begin
									user_state	<=	#Tp	gen_read_req;
									write_req	<=	#Tp	1'b0;	
								end
							if(w_data_valid)
								begin
									rom_addr	<=	#Tp	rom_addr+1'b1;
								end
						end					
					gen_read_req:
						begin
							burst_len	<=	#Tp	9'd256;		//read 8 word to sdram
							sys_addr	<=	#Tp	22'h00000f;	//from addr at 0xf
							read_req	<=	#Tp	1'b1;
							ram_addr	<=	#Tp	9'd0;
							user_state	<=	#Tp	wait_read_ack;							
						end				
					wait_read_ack:
						begin
							if(read_ack)
								begin
									user_state	<=	#Tp	idle;
									read_req	<=	#Tp	1'b0;	
									burst_len	<=	#Tp	9'd0;		
									sys_addr	<=	#Tp	22'h000000;	
								end
							if(r_data_valid)
								begin
									ram_addr	<=	#Tp	ram_addr+1'b1;
								end	
						end					
					idle:
						begin
							user_state	<=	#Tp	idle;
						end
				endcase
			end
	end

endmodule