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sdram 控制器的verilog 实现

Analysis & Synthesis Status : Successful - Tue Sep 16 09:28:04 2008
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
Revision Name : top
Top-level Entity Name : top
Family : Cyclone
Total logic elements : 545
Total pins : 45
Total virtual pins : 0
Total memory bits : 12,288
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 1
Total DLLs : N/A until Partition Merge