singal.do.bak

sdram 控制器的verilog 实现

virtual type {
{4'b0000 c_IDLE}
{4'b0001 c_AR}
{4'b0010 c_tRFC}
{4'b0011 c_RW_AR}
{4'b0100 c_RW_tRFC}
{4'b0101 c_ACTIVE}
{4'b0110 c_tRCD}
{4'b0111 c_READ}
{4'b1000 c_RD_DATA}
{4'b1001 c_R_PRE}
{4'b1010 c_R_tRP}
{4'b1011 c_WRITE}
{4'b1100 c_WR_DATA}
{4'b1101 c_W_PRE}
{4'b1110 c_W_tRP}
} c_FSM_TYPE;

virtual type {
{3'b000 i_NOP}
{3'b001 i_PRE}
{3'b010 i_tRP}
{3'b011 i_AR}
{3'b100 i_tRFC}
{3'b101 i_MRS}
{3'b110 i_tMRD}
{3'b111 i_ready}
} i_FSM_TYPE;

virtual type {
{6'b000001 wait_setup}
{6'b000010 gen_write_req}
{6'b000100 wait_write_ack}
{6'b001000 gen_read_req}
{6'b010000 wait_read_ack}
{6'b100000 idle}
} u_FSM_TYPE;

virtual function {(i_FSM_TYPE)/tb/top_inst/b2v_inst/U1/i_state} i_state_new;
virtual function {(c_FSM_TYPE)/tb/top_inst/b2v_inst/U0/c_state} c_state_new;
virtual function {(c_FSM_TYPE)/tb/top_inst/b2v_inst3/user_state} u_state_new;

view wave
add wave *

#----------------to see internal signal----------------
add wave /tb/top_inst/b2v_inst3/u_state_new
#output
add wave /tb/top_inst/b2v_inst3/read_req
add wave /tb/top_inst/b2v_inst3/write_req
add wave /tb/top_inst/b2v_inst3/burst_len
add wave /tb/top_inst/b2v_inst3/sys_addr
add wave /tb/top_inst/b2v_inst3/data_to_sdram
#input
add wave /tb/top_inst/b2v_inst3/setup_done
add wave /tb/top_inst/b2v_inst3/read_ack
add wave /tb/top_inst/b2v_inst3/write_ack
add wave /tb/top_inst/b2v_inst3/r_data_valid
add wave /tb/top_inst/b2v_inst3/w_data_valid
add wave /tb/top_inst/b2v_inst3/data_from_sdram
add wave /tb/top_inst/b2v_inst3/ram_addr
add wave /tb/top_inst/b2v_inst3/rom_addr
################################################################
add wave /tb/top_inst/b2v_inst/U1/i_state_new
################################################################
add wave /tb/top_inst/b2v_inst/U0/c_state_new
run -all