refresh.v

来自「sdram 控制器的verilog 实现」· Verilog 代码 · 共 54 行

`timescale 1ns/100ps
module refresh(
				clk,
				rst_n,
				init_done,
				refresh_ack,
				refresh_req
				);
input clk;
input rst_n;
input init_done;
input refresh_ack;
output reg refresh_req;
//----------------parameter declare-------------
`ifdef simulation
parameter cnt_50 = 100;                // 50 Mhz clock
`else				
parameter cnt_50 = 780;                // 50 Mhz clock
`endif   	
parameter COUNT = cnt_50;              // set for 50M
parameter Tp=2;						   // set for uTco delay
//----------------variable declare---------------
reg[9:0] refresh_cnt;					//refresh counter

//----------------main code--------------------
always@(posedge clk)
	begin
		if(!rst_n)
			begin
				refresh_req		<=#Tp	1'b0;
				refresh_cnt		<=#Tp	10'd0;
			end
		else
			begin
				if(init_done && (refresh_cnt!=COUNT))
					begin
						refresh_cnt		<=#Tp	refresh_cnt+1'b1;
					end
				//--------if reach the time generate req signal-------------	
				if(refresh_cnt==COUNT)
					begin
						refresh_req		<=#Tp	1'b1;
					end
				//-------if receive	the ack signal clear the req signal and refresh cnt
				//如果没有收到应答信号，则一直保持请求信号有效
				if(refresh_ack)
					begin
						refresh_req		<=#Tp	1'b0;
						refresh_cnt		<=#Tp	10'd0;
					end
			end
	end
				
endmodule