top.map.rpt

sdram 控制器的verilog 实现

; Device                                                                         ; EP1C6Q240C8        ;                    ;
; Top-level entity name                                                          ; top                ; top                ;
; Family name                                                                    ; Cyclone            ; Stratix II         ;
; Type of Retiming Performed During Resynthesis                                  ; Full               ;                    ;
; Resynthesis Optimization Effort                                                ; Normal             ;                    ;
; Physical Synthesis Level for Resynthesis                                       ; Normal             ;                    ;
; Use Generated Physical Constraints File                                        ; On                 ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                              ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                        ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                        ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------------+
; pll/pll_50.v                     ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/pll/pll_50.v                          ;
; delay_reset/counter.v            ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/delay_reset/counter.v                 ;
; delay_reset/reset.bdf            ; yes             ; User Block Diagram/Schematic File  ; E:/pratice/verilog/sdram_controller/sdram_all/delay_reset/reset.bdf                 ;
; top.bdf                          ; yes             ; User Block Diagram/Schematic File  ; E:/pratice/verilog/sdram_controller/sdram_all/top.bdf                               ;
; source_user/ram512.v             ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/source_user/ram512.v                  ;
; source_user/rom256.v             ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/source_user/rom256.v                  ;
; source_user/user_interface.v     ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/source_user/user_interface.v          ;
; source_sdram/init_fsm.v          ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/init_fsm.v               ;
; source_sdram/main_fsm.v          ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/main_fsm.v               ;
; source_sdram/refresh.v           ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/refresh.v                ;
; source_sdram/sdr_par.v           ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/sdr_par.v                ;
; source_sdram/sdr_sig.v           ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/sdr_sig.v                ;
; source_sdram/sdram_top.v         ; yes             ; User Verilog HDL File              ; E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/sdram_top.v              ;
; altpll.tdf                       ; yes             ; Megafunction                       ; d:/program files/quartus7_2/quartus/libraries/megafunctions/altpll.tdf              ;
; aglobal72.inc                    ; yes             ; Megafunction                       ; d:/program files/quartus7_2/quartus/libraries/megafunctions/aglobal72.inc           ;
; stratix_pll.inc                  ; yes             ; Megafunction                       ; d:/program files/quartus7_2/quartus/libraries/megafunctions/stratix_pll.inc         ;
; stratixii_pll.inc                ; yes             ; Megafunction                       ; d:/program files/quartus7_2/quartus/libraries/megafunctions/stratixii_pll.inc       ;
; cycloneii_pll.inc                ; yes             ; Megafunction                       ; d:/program files/quartus7_2/quartus/libraries/megafunctions/cycloneii_pll.inc       ;