top.map.rpt

sdram 控制器的verilog 实现

Analysis & Synthesis report for top
Tue Sep 16 09:28:04 2008
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |top|user_interface:inst3|user_state
  9. Registers Protected by Synthesis
 10. Registers Removed During Synthesis
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for sdram_top:inst|init_fsm:U1
 15. Source assignments for reset:inst2|counter:inst|lpm_counter:lpm_counter_component
 16. Source assignments for user_interface:inst3|rom256:rom256_inst|altsyncram:altsyncram_component|altsyncram_2361:auto_generated|altsyncram_fk72:altsyncram1
 17. Source assignments for user_interface:inst3|rom256:rom256_inst|altsyncram:altsyncram_component|altsyncram_2361:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
 18. Source assignments for user_interface:inst3|ram512:ram512_inst|altsyncram:altsyncram_component|altsyncram_0qe1:auto_generated|altsyncram_e9a2:altsyncram1
 19. Source assignments for user_interface:inst3|ram512:ram512_inst|altsyncram:altsyncram_component|altsyncram_0qe1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
 20. Source assignments for sld_hub:sld_hub_inst
 21. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 22. Parameter Settings for User Entity Instance: sdram_top:inst|main_fsm:U0
 23. Parameter Settings for User Entity Instance: sdram_top:inst|init_fsm:U1
 24. Parameter Settings for User Entity Instance: sdram_top:inst|refresh:U2
 25. Parameter Settings for User Entity Instance: sdram_top:inst|sdr_sig:U3
 26. Parameter Settings for User Entity Instance: pll_50:inst1|altpll:altpll_component
 27. Parameter Settings for User Entity Instance: reset:inst2|counter:inst|lpm_counter:lpm_counter_component
 28. Parameter Settings for User Entity Instance: user_interface:inst3
 29. Parameter Settings for User Entity Instance: user_interface:inst3|rom256:rom256_inst|altsyncram:altsyncram_component
 30. Parameter Settings for User Entity Instance: user_interface:inst3|rom256:rom256_inst|altsyncram:altsyncram_component|altsyncram_2361:auto_generated|sld_mod_ram_rom:mgl_prim2
 31. Parameter Settings for User Entity Instance: user_interface:inst3|ram512:ram512_inst|altsyncram:altsyncram_component
 32. Parameter Settings for User Entity Instance: user_interface:inst3|ram512:ram512_inst|altsyncram:altsyncram_component|altsyncram_0qe1:auto_generated|sld_mod_ram_rom:mgl_prim2
 33. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 34. In-System Memory Content Editor Settings
 35. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 16 09:28:04 2008         ;
; Quartus II Version          ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name               ; top                                           ;
; Top-level Entity Name       ; top                                           ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 545                                           ;
; Total pins                  ; 45                                            ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 12,288                                        ;
; DSP block 9-bit elements    ; N/A until Partition Merge                     ;
; Total PLLs                  ; 1                                             ;
; Total DLLs                  ; N/A until Partition Merge                     ;
+-----------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+