top.fit.rpt

sdram 控制器的verilog 实现

Fitter report for top
Tue Sep 16 09:28:20 2008
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. Bidir Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. PLL Summary
 12. PLL Usage
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Control Signals
 18. Global & Other Fast Signals
 19. Non-Global High Fan-Out Signals
 20. Fitter RAM Summary
 21. Interconnect Usage Summary
 22. LAB Logic Elements
 23. LAB-wide Signals
 24. LAB Signals Sourced
 25. LAB Signals Sourced Out
 26. LAB Distinct Inputs
 27. Fitter Device Options
 28. Advanced Data - General
 29. Advanced Data - Placement Preparation
 30. Advanced Data - Placement
 31. Advanced Data - Routing
 32. Fitter Messages
 33. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Fitter Summary                                                        ;
+-----------------------+-----------------------------------------------+
; Fitter Status         ; Successful - Tue Sep 16 09:28:20 2008         ;
; Quartus II Version    ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name         ; top                                           ;
; Top-level Entity Name ; top                                           ;
; Family                ; Cyclone                                       ;
; Device                ; EP1C6Q240C8                                   ;
; Timing Models         ; Final                                         ;
; Total logic elements  ; 528 / 5,980 ( 9 % )                           ;
; Total pins            ; 45 / 185 ( 24 % )                             ;
; Total virtual pins    ; 0                                             ;
; Total memory bits     ; 12,288 / 92,160 ( 13 % )                      ;
; Total PLLs            ; 1 / 2 ( 50 % )                                ;
+-----------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP1C6Q240C8                    ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;