top.fit.summary

sdram 控制器的verilog 实现

Fitter Status : Successful - Tue Sep 16 09:28:20 2008
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
Revision Name : top
Top-level Entity Name : top
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 528 / 5,980 ( 9 % )
Total pins : 45 / 185 ( 24 % )
Total virtual pins : 0
Total memory bits : 12,288 / 92,160 ( 13 % )
Total PLLs : 1 / 2 ( 50 % )