top_nativelink_simulation.rpt

sdram 控制器的verilog 实现

ModelSim-Altera Info: # {3'b111 i_ready}
ModelSim-Altera Info: # } i_FSM_TYPE;
ModelSim-Altera Info: # 
ModelSim-Altera Info: # virtual type {
ModelSim-Altera Info: # {6'b000001 wait_setup}
ModelSim-Altera Info: # {6'b000010 gen_write_req}
ModelSim-Altera Info: # {6'b000100 wait_write_ack}
ModelSim-Altera Info: # {6'b001000 gen_read_req}
ModelSim-Altera Info: # {6'b010000 wait_read_ack}
ModelSim-Altera Info: # {6'b100000 idle}
ModelSim-Altera Info: # } u_FSM_TYPE;
ModelSim-Altera Info: # 
ModelSim-Altera Info: # virtual function {(i_FSM_TYPE)/tb/top_inst/b2v_inst/U1/i_state} i_state_new;
ModelSim-Altera Info: # /tb/top_inst/b2v_inst/U1/i_state_new
ModelSim-Altera Info: # virtual function {(c_FSM_TYPE)/tb/top_inst/b2v_inst/U0/c_state} c_state_new;
ModelSim-Altera Info: # /tb/top_inst/b2v_inst/U0/c_state_new
ModelSim-Altera Info: # virtual function {(u_FSM_TYPE)/tb/top_inst/b2v_inst3/user_state} u_state_new;
ModelSim-Altera Info: # /tb/top_inst/b2v_inst3/u_state_new
ModelSim-Altera Info: # 
ModelSim-Altera Info: # view wave
ModelSim-Altera Info: # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
ModelSim-Altera Info: # add wave *
ModelSim-Altera Info: # 
ModelSim-Altera Info: #----------------to see internal signal----------------
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/u_state_new
ModelSim-Altera Info: #output
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/read_req
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/write_req
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/burst_len
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/sys_addr
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/data_to_sdram
ModelSim-Altera Info: #input
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/setup_done
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/read_ack
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/write_ack
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/r_data_valid
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/w_data_valid
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/data_from_sdram
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/ram_addr
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst3/rom_addr
ModelSim-Altera Info: ################################################################
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst/U1/i_state_new
ModelSim-Altera Info: ################################################################
ModelSim-Altera Info: # add wave /tb/top_inst/b2v_inst/U0/c_state_new
ModelSim-Altera Info: # run -all
ModelSim-Altera Info: # Warning: read_during_write_mode_mixed_ports is assumed as   OLD_DATA
ModelSim-Altera Info: # Warning: read_during_write_mode_mixed_ports is assumed as   OLD_DATA
ModelSim-Altera Info: # the rst_n signal invaild at time=200ns
ModelSim-Altera Info: # Break at E:/pratice/verilog/sdram_controller/sdram_all/testbench/testbench.v line 60
ModelSim-Altera Info: # Simulation Breakpoint: Break at E:/pratice/verilog/sdram_controller/sdram_all/testbench/testbench.v line 60
ModelSim-Altera Info: # MACRO E:\pratice\verilog\sdram_controller\sdram_all\testbench\singal.do PAUSED at line 67
ModelSim-Altera Info: do E:/pratice/verilog/sdram_controller/sdram_all/simulation/modelsim/rtl_wave.do
ModelSim-Altera Info: # onerror {resume}
ModelSim-Altera Info: # quietly WaveActivateNextPane {} 0
ModelSim-Altera Info: # virtual type { \
ModelSim-Altera Info: # {0x1 wait_setup}\
ModelSim-Altera Info: # {0x2 gen_write_req}\
ModelSim-Altera Info: # {0x4 wait_write_ack}\
ModelSim-Altera Info: # {0x8 gen_read_req}\
ModelSim-Altera Info: # {0x10 wait_read_ack}\
ModelSim-Altera Info: # {0x20 idle}\
ModelSim-Altera Info: # } u_FSM_TYPE
ModelSim-Altera Info: # virtual type { \
ModelSim-Altera Info: # i_NOP\
ModelSim-Altera Info: # i_PRE\
ModelSim-Altera Info: # i_tRP\
ModelSim-Altera Info: # i_AR\
ModelSim-Altera Info: # i_tRFC\
ModelSim-Altera Info: # i_MRS\
ModelSim-Altera Info: # i_tMRD\
ModelSim-Altera Info: # i_ready\
ModelSim-Altera Info: # } i_FSM_TYPE
ModelSim-Altera Error: # ** Error: A different user-defined type: i_FSM_TYPE already exists.
ModelSim-Altera Info: # Executing ONERROR command at macro E:\pratice\verilog\sdram_controller\sdram_all\simulation\modelsim\rtl_wave.do line 20
ModelSim-Altera Info: # virtual type { \
ModelSim-Altera Info: # c_IDLE\
ModelSim-Altera Info: # c_AR\
ModelSim-Altera Info: # c_tRFC\
ModelSim-Altera Info: # c_RW_AR\
ModelSim-Altera Info: # c_RW_tRFC\
ModelSim-Altera Info: # c_ACTIVE\
ModelSim-Altera Info: # c_tRCD\
ModelSim-Altera Info: # c_READ\
ModelSim-Altera Info: # c_RD_DATA\
ModelSim-Altera Info: # c_R_PRE\
ModelSim-Altera Info: # c_R_tRP\
ModelSim-Altera Info: # c_WRITE\
ModelSim-Altera Info: # c_WR_DATA\
ModelSim-Altera Info: # c_W_PRE\
ModelSim-Altera Info: # c_W_tRP\
ModelSim-Altera Info: # } c_FSM_TYPE
ModelSim-Altera Error: # ** Error: A different user-defined type: c_FSM_TYPE already exists.
ModelSim-Altera Info: # Executing ONERROR command at macro E:\pratice\verilog\sdram_controller\sdram_all\simulation\modelsim\rtl_wave.do line 37
ModelSim-Altera Info: # quietly virtual function -install /tb/top_inst/b2v_inst3 -env /tb { (c_FSM_TYPE)/tb/top_inst/b2v_inst3/user_state} u_state_new
ModelSim-Altera Info: # quietly virtual function -install /tb/top_inst/b2v_inst/U1 -env /tb { (i_FSM_TYPE)/tb/top_inst/b2v_inst/U1/i_state} i_state_new
ModelSim-Altera Info: # quietly virtual function -install /tb/top_inst/b2v_inst/U0 -env /tb { (c_FSM_TYPE)/tb/top_inst/b2v_inst/U0/c_state} c_state_new
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/clk
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/rst_n
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/sdram_cke
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/sdram_cs_n
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/sdram_ras_n
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/sdram_cas_n
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/sdram_we_n
ModelSim-Altera Info: # add wave -noupdate -format Literal /tb/sdram_ba
ModelSim-Altera Info: # add wave -noupdate -format Literal /tb/sdram_dqm
ModelSim-Altera Info: # add wave -noupdate -format Literal -radix hexadecimal /tb/sdram_data
ModelSim-Altera Info: # add wave -noupdate -format Literal -radix hexadecimal /tb/sdram_addr
ModelSim-Altera Info: # add wave -noupdate -format Literal /tb/top_inst/b2v_inst3/u_state_new
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/top_inst/b2v_inst3/read_ack
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/top_inst/b2v_inst3/read_req
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/top_inst/b2v_inst3/r_data_valid
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/top_inst/b2v_inst3/write_ack
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/top_inst/b2v_inst3/write_req
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/top_inst/b2v_inst3/w_data_valid
ModelSim-Altera Info: # add wave -noupdate -format Literal -radix unsigned /tb/top_inst/b2v_inst3/burst_len
ModelSim-Altera Info: # add wave -noupdate -format Literal -radix hexadecimal /tb/top_inst/b2v_inst3/sys_addr
ModelSim-Altera Info: # add wave -noupdate -format Literal -radix hexadecimal /tb/top_inst/b2v_inst3/data_to_sdram
ModelSim-Altera Info: # add wave -noupdate -format Logic /tb/top_inst/b2v_inst3/setup_done
ModelSim-Altera Info: # add wave -noupdate -format Literal -radix hexadecimal /tb/top_inst/b2v_inst3/data_from_sdram
ModelSim-Altera Info: # add wave -noupdate -format Literal -radix unsigned /tb/top_inst/b2v_inst3/ram_addr
ModelSim-Altera Info: # add wave -noupdate -format Literal -radix unsigned /tb/top_inst/b2v_inst3/rom_addr
ModelSim-Altera Info: # add wave -noupdate -format Literal /tb/top_inst/b2v_inst/U1/i_state_new
ModelSim-Altera Info: # add wave -noupdate -format Literal /tb/top_inst/b2v_inst/U0/c_state_new
ModelSim-Altera Info: # TreeUpdate [SetDefaultTree]
ModelSim-Altera Info: # WaveRestoreCursors {{Cursor 1} {1530000 ps} 0} {{Cursor 2} {1670000 ps} 0} {{Cursor 3} {1770000 ps} 0} {{Cursor 4} {1330000 ps} 0} {{Cursor 5} {1430000 ps} 0} {{Cursor 6} {1810000 ps} 0}
ModelSim-Altera Info: # configure wave -namecolwidth 295
ModelSim-Altera Info: # configure wave -valuecolwidth 100
ModelSim-Altera Info: # configure wave -justifyvalue left
ModelSim-Altera Info: # configure wave -signalnamewidth 0
ModelSim-Altera Info: # configure wave -snapdistance 10
ModelSim-Altera Info: # configure wave -datasetprefix 0
ModelSim-Altera Info: # configure wave -rowmargin 4
ModelSim-Altera Info: # configure wave -childrowmargin 2
ModelSim-Altera Info: # configure wave -gridoffset 0
ModelSim-Altera Info: # configure wave -gridperiod 1
ModelSim-Altera Info: # configure wave -griddelta 40
ModelSim-Altera Info: # configure wave -timeline 0
ModelSim-Altera Info: # update
ModelSim-Altera Info: # WaveRestoreZoom {1595163 ps} {2090588 ps}
Error: NativeLink simulation flow was NOT successful



================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode:  NONE
Nativelink TCL script failed with errorInfo:  package "rdb21" isn't loaded statically
    while executing
"load "" rdb21 "