sd_state.vhd

sdram接口的vhdl实现,适用于lattice的FPGA

-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
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--                     Lattice Semiconductor Corporation
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-- Revision History :
-----------------------------------------------------------------------
-- Ver  | Author    | Mod. Date | Changes Made:
-----------------------------------------------------------------------
-- 0.1  | kam       | 9/3/99    | birth
-- 1.0  | kam       | ------    | Release
-----------------------------------------------------------------------

-- This is the state machine for the synchronous DRAM controller.  It 
-- outputs 2 binary encoded vectors one indicates the kind of
-- sdram cycle requested and the second indicates the state.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sd_state is
     port (sdram_cs_l:      in   std_logic;
           cmnd_cycle_req:  in   std_logic;
           rfrsh_req:       in   std_logic;
           clk:             in   std_logic;
           rst_l:           in   std_logic;
           sdram_cycle:     out  std_logic_vector(3 downto 0);
           state_cntr:      out  std_logic_vector(3 downto 0));
end sd_state;

architecture RTL of sd_state is

  -- state parameters
  constant idl_cycle:  std_logic_vector(3 downto 0) := "0001";
  constant cmd_cycle:  std_logic_vector(3 downto 0) := "0010";
  constant dat_cycle:  std_logic_vector(3 downto 0) := "0100";
  constant rfr_cycle:  std_logic_vector(3 downto 0) := "1000";
  signal sdram_cycle_sig: std_logic_vector(3 downto 0);
  signal state_cntr_sig: std_logic_vector(3 downto 0);

  begin
    sdram_cycle <= sdram_cycle_sig;
    state_cntr <= state_cntr_sig;

  state_machine: process (clk, rst_l, sdram_cycle_sig)
  begin
  
    if(rst_l = '0') then
      sdram_cycle_sig <= idl_cycle after 1 ns;
    elsif rising_edge(clk) then
      case sdram_cycle_sig is
         when idl_cycle => if(cmnd_cycle_req = '1') then
                              sdram_cycle_sig <= cmd_cycle after 1 ns;
                           elsif (sdram_cs_l = '0') then
                              sdram_cycle_sig <= dat_cycle after 1 ns;
                           elsif (rfrsh_req = '1') then
                              sdram_cycle_sig <= rfr_cycle after 1 ns;
                           else
                              sdram_cycle_sig <= idl_cycle after 1 ns;
                           end if;
  
         when cmd_cycle => if(state_cntr_sig(3) = '1') then
                             sdram_cycle_sig <= idl_cycle after 1 ns;
                           end if;

         when dat_cycle => if(sdram_cs_l = '1') then
                             sdram_cycle_sig <= idl_cycle after 1 ns;
                           end if;

         when rfr_cycle => if(state_cntr_sig = "1100") then
                             sdram_cycle_sig <= idl_cycle after 1 ns;
                           end if;

         when others => sdram_cycle_sig <= "0000" after 1 ns; 

      end case;
    end if;
  end process state_machine;

  cycle_counter: process(clk, rst_l, sdram_cycle_sig, state_cntr_sig)
  begin

    if (rst_l =  '0') then
       state_cntr_sig <= "0000" after 1 ns;
    elsif rising_edge(clk) then
       if(sdram_cycle_sig(0) = '0') then
          state_cntr_sig <= state_cntr_sig + "0001" after 1 ns;
       else
          state_cntr_sig <= "0000" after 1 ns;
       end if;
    end if;
  end process cycle_counter;

end architecture RTL;