控制器ssram.vhdl

USB源代码

--控制器SSRAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity usbf_mem_arb is  --实体声明
generic(SSRAM_HADR:integer:=14);
port(phy_clk,wclk,rst:in std_logic;
    sram_adr:buffer std_logic_vector(SSRAM_HADR downto 0);
    sram_din:in std_logic_vector(31 downto 0);
    sram_dout:buffer std_logic_vector(31 downto 0);
    sram_re,sram_weut std_logic;
    --SSRAM接口
    madr:in std_logic_vector(SSRAM_HADR downto 0);
    mdoutut std_logic_vector(31 downto 0);
    mdin:in std_logic_vector(31 downto 0);
    mwe:in std_logic;
    mreq:in std_logic;
    mack:buffer stdlogic;
    --内部DMA操作接口
    wadr:in std_logic_vector(SSRAM_HADR downto 0);
    wdoutut std_logic_vector(31 downto 0);
    wdin:in std_logic_vector(31 downto 0);
    wwe:in std_logic;
    wreq:in std_logic;
    wack:buffer std_logic    --应用模块的wishbone接口
      );
    end entity
    
    architecture arch_of_mem_arb of usbf_mem_arb is
    signal wsel:std_logic;
    signal mcy:stdlogic;
    signal wack_r:std_logic;
    begin
    wsel<=(wreq or wack)and not(mreq);
    --对SRAM数据输出
    process(wsel,wdin,mdin)
    begin
    if(wsel='1')then
    sram_dout<=wdin;
    else sram_dout<=mdin;
    end if;
    end process;
    --sram地址线输出
    process(wsel,wadr,madr)
    begin
    if(wsel='1')then
        sram_adr<=wadr;
    else sram_adr<=madr;
    end if;
    end process;
    --sram写操作使能控制
    process(wsel,wwe,wreq,mwe,mcyc)begin
    if(wsel='1')then
        sram_we<=wreq and wwe;
    else sram_we<=mwe and mcc;
    end if;
    end process;

    sram_re<='1';
    mdout<=sram_din;
    mack<=mreq;
    mcyc<=mack;
    --应用模块之间的wishbone接口
    wdout<=sram_din;
    wack<=wack_r and not(mreq);
    
    process(rst,phy_clk)begin
            if(rst='0')then
              wack_r<='0';
            else if(ph_clk' event and phy_clk='1')then
            wack_r<=wreq and not(mreq)and not(wack);
            end if;
    end process;
    end architecture;