控制器wishbone.vhdl

USB源代码

--控制器WISHBONE
--file:usb_wishbone.vhd
    library ieee
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity usbf_wb is
    generic(USBF_UFC_HADR:integer:=17);
    port(wb_clk,phy_clk:in std_logic;
        rst:in std_logic;
        wb_addr_i:in std_logic_vector(USBF_UFC_HDR downto 0);
        wb_data_i:in std_logic_vector(31 downto 0);
        wb_data_o:buffer std_logic_vector(31 downto 0);
        wb_ack_o:buffer std_logic;
        wb_we_i:in std_logic;
        wb_stb_i:in std_logic;
        wb_cyc_i:in std_logic:
  --应用程序的WISHBONE接口
                
    ma_adrut std_logic_vector(USBF_UFC_HADR downto 0);
    ma_doutut std_logic_vector(31 downto 0);  
    ma_dinut std_logic_vector(31 downto 0); 
    ma_we:buffer std_logic_vector(31 wownto 0);
    ma_req:buffer std_logic;
    ma_ack:in std_logic;
  --存储器仲裁器接口
      
    rf_re:buffer std_logic;
    rf_we:out std_logic;
    rf_din:in std_logic_vector(31 downto 0);
    rf_dout:out std_logic_vector(31 downto 0);
    );
    end entity;

    architecture arch_usbf_wb of usbf_wb is
    constant IDLE:std_logic_vector(5 downto 0):="000001";
    constant MA_WR:std_logic_vector(5 downto 0):="000010";
    constant MA_RD:Std_logic_vector(5 downto 0):="000100";
    constant WO:Std_logic_vector(5 downto 0):="001000";
    constant W1:Std_logic_vector(5 downto 0):="010000";
    constant W2:Std_logic_vector(5 downto 0):="100000";
    
    signal state,next_state:std_logic_vector(5 downto 0);
                                                          
    signal wb_req_sl:std_logic;
    signal wb_ack_d,wb_ack_sl,wb_ack_sla,wb_ack_s2:std_logic;
    signal rf_we_d:std_logic;
--状态机状态
    begin
    ma_adr<=wb_addr_i;
    ma_dout<=wb_data_i;
    rf_dout<=wb_data_i;
--数据，地址由应用模块驱动，输出至存储器或内部存储器
    process(wb_clk)begin
          if(wb_clk'evevt and wb_clk='1')then
          if(not(wb_addr_i(17)0='1')then
                wb_data_o<=rf_din;
          else wb_data_o<=ma_din;
          end if;
          end if;
    end process;
--数据通道，仲裁数据输入来源是寄存器或储存器
    process(phy_clk)begin
          if phy_clk'event and phy_clk='1'then
          wb_req_s1<=(wb_std_i nd wb_cyc_i);
          end if;
    end process;
--wishbone 请求
    process(wb_clk)begin
          if wb_clk'event and wb_clk='1' then
          wb_ack_sl<=wb_ack_d;
          end if;
    end process;

    process(wb_clk)begin
          if wb_clk'event and wb_clk='1' then 
          wb_ack_o<=(wb_ack_s1 and not(wb_ack_s2)and not(wb_ack_0));
          end if;
    end process;
          
    process(wb_clk)begin
          if wb_clk'event and wb_clk='1' then 
          wb_ack_s2<=wb_ack_s1a;
          end if;
    end process;

    process(wb_clk)begin
          if wb_clk'event and wb_clk='1' then 
          wb_ck_s2<=wb_ack_s1a;
          end if;
    end process;
    --内部寄存器写使能驱动
    
    rf_we<=rf_we_d;
    
    process(phy_clk,rst)begin
          if(rst='0')then
                state<=IDLE;
          elsif wb_clk'event and wb_clk='1' then 
                state<=next_state;
          end if;
    end process;

    process(state,wb_req_s1,wb_addr_i,ma_ack,wb_we_i)
          begin
          next_state<=state;
          ma_req<='0';
          ma_we<='0';
          wb_ack_d<='0';
          rf_re<='0';
          rf_we_d<='0';

      case state is  --状态机状态转移
          when IDLE=>
          if(wb_req_s1='1' and wb_addr_i(17)='0'and wb_we_i='1')then
                ma_req<='1';
                ma_we<='1';
                next_state<=M_WR;    --存储器写状态
          end if;
          if(wb_req_s1='1' and wb_addr_i(17)='0'and wb_we_i='0')then
                ma_req<='1';
                next_state<=MA_WR;  --存储器读状态
          end if;
          if(wb_req_s1='1' and wb_addr_i(12)='0'and wb_we_i='1')then
                rf_we_d<='1';
                next_state<=W0;      --寄存器写状态
          end if;
          if(wb_req_s1='1' and wb_addr_i(12)='0'and wb_we_i='0')then
                rf_re<='1';
                next_state<=W0;      --寄存器读状态
          end if;
      
          when MA_WR=>
            if(ma_ack='0')then
                ma_req<='1';
                ma_we<='1';
            else
                wb_ack_d<='1';
                next_state<=W1;
            end if;
                          
          when MA_RD=>
            if(ma_ack='0') then
                ma_req<='1';
            else
                wb_ack_d<='1';
                next_state<=W1;
            end if;

          when W0=>
            wb_ack_d<='1';
            next_state<=W1;          --W1

          when W1=>
            next_state<=W2;          --W2

          when W2=>
            next_state<=IDLE;        --IDLE

          when others=>
            null;
          end case;
      end process;