📄 mux.tan.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 10 21:13:45 2008 " "Info: Processing started: Mon Nov 10 21:13:45 2008" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "addr\[1\] Mout 19.161 ns Longest " "Info: Longest tpd from source pin \"addr\[1\]\" to destination pin \"Mout\" is 19.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns addr\[1\] 1 PIN PIN_159 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_159; Fanout = 3; PIN Node = 'addr\[1\]'" { } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr[1] } "NODE_NAME" } } { "mux.v" "" { Text "D:/Program Files/quartus/Design/logic_design/mux/mux.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(10.327 ns) + CELL(0.590 ns) 12.386 ns Mux0~13 2 COMB LC_X16_Y1_N2 1 " "Info: 2: + IC(10.327 ns) + CELL(0.590 ns) = 12.386 ns; Loc. = LC_X16_Y1_N2; Fanout = 1; COMB Node = 'Mux0~13'" { } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "10.917 ns" { addr[1] Mux0~13 } "NODE_NAME" } } { "mux.v" "" { Text "D:/Program Files/quartus/Design/logic_design/mux/mux.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.424 ns) + CELL(0.590 ns) 13.400 ns Mux0~14 3 COMB LC_X16_Y1_N6 1 " "Info: 3: + IC(0.424 ns) + CELL(0.590 ns) = 13.400 ns; Loc. = LC_X16_Y1_N6; Fanout = 1; COMB Node = 'Mux0~14'" { } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.014 ns" { Mux0~13 Mux0~14 } "NODE_NAME" } } { "mux.v" "" { Text "D:/Program Files/quartus/Design/logic_design/mux/mux.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.590 ns) 14.419 ns Mout~32 4 COMB LC_X16_Y1_N4 1 " "Info: 4: + IC(0.429 ns) + CELL(0.590 ns) = 14.419 ns; Loc. = LC_X16_Y1_N4; Fanout = 1; COMB Node = 'Mout~32'" { } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.019 ns" { Mux0~14 Mout~32 } "NODE_NAME" } } { "mux.v" "" { Text "D:/Program Files/quartus/Design/logic_design/mux/mux.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.634 ns) + CELL(2.108 ns) 19.161 ns Mout 5 PIN PIN_100 0 " "Info: 5: + IC(2.634 ns) + CELL(2.108 ns) = 19.161 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'Mout'" { } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.742 ns" { Mout~32 Mout } "NODE_NAME" } } { "mux.v" "" { Text "D:/Program Files/quartus/Design/logic_design/mux/mux.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.347 ns ( 27.91 % ) " "Info: Total cell delay = 5.347 ns ( 27.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.814 ns ( 72.09 % ) " "Info: Total interconnect delay = 13.814 ns ( 72.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "19.161 ns" { addr[1] Mux0~13 Mux0~14 Mout~32 Mout } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "19.161 ns" { addr[1] addr[1]~out0 Mux0~13 Mux0~14 Mout~32 Mout } { 0.000ns 0.000ns 10.327ns 0.424ns 0.429ns 2.634ns } { 0.000ns 1.469ns 0.590ns 0.590ns 0.590ns 2.108ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 10 21:13:46 2008 " "Info: Processing ended: Mon Nov 10 21:13:46 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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