mux.sim.rpt

多路选择器是一个多输入

The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                              ;
+-----------------------------------------------------------+-----------------------------------------------------------+------------------+
; Node Name                                                 ; Output Port Name                                          ; Output Port Type ;
+-----------------------------------------------------------+-----------------------------------------------------------+------------------+
; |mux|Mout~0                                               ; |mux|Mout~0                                               ; out              ;
; |mux|addr[0]                                              ; |mux|addr[0]                                              ; out              ;
; |mux|addr[1]                                              ; |mux|addr[1]                                              ; out              ;
; |mux|addr[2]                                              ; |mux|addr[2]                                              ; out              ;
; |mux|in1                                                  ; |mux|in1                                                  ; out              ;
; |mux|in2                                                  ; |mux|in2                                                  ; out              ;
; |mux|in3                                                  ; |mux|in3                                                  ; out              ;
; |mux|in4                                                  ; |mux|in4                                                  ; out              ;
; |mux|in5                                                  ; |mux|in5                                                  ; out              ;
; |mux|in6                                                  ; |mux|in6                                                  ; out              ;
; |mux|in7                                                  ; |mux|in7                                                  ; out              ;
; |mux|in8                                                  ; |mux|in8                                                  ; out              ;
; |mux|Mout                                                 ; |mux|Mout                                                 ; pin_out          ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|result_node[0]~0 ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|result_node[0]~0 ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~0              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~0              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|result_node[0]~1 ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|result_node[0]~1 ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|result_node[0]   ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|result_node[0]   ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~1              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~1              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~2              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~2              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result36w~0    ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result36w~0    ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~3              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~3              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~4              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~4              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result36w~1    ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result36w~1    ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result36w      ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result36w      ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~5              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~5              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~6              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~6              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result37w~0    ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result37w~0    ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~7              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~7              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~8              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~8              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result37w~1    ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result37w~1    ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result37w      ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result37w      ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~9              ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~9              ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~10             ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~10             ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~11             ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~11             ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~12             ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~12             ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result44w~1    ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result44w~1    ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result44w      ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result44w      ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~13             ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~13             ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~14             ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~14             ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~15             ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~15             ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result65w~0    ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result65w~0    ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~16             ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|_~16             ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result65w~1    ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result65w~1    ; out0             ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result65w      ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result65w      ; out0             ;
+-----------------------------------------------------------+-----------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                           ;
+--------------------------------------------------------+--------------------------------------------------------+------------------+
; Node Name                                              ; Output Port Name                                       ; Output Port Type ;
+--------------------------------------------------------+--------------------------------------------------------+------------------+
; |mux|ncs                                               ; |mux|ncs                                               ; out              ;
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result44w~0 ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result44w~0 ; out0             ;
+--------------------------------------------------------+--------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                           ;
+--------------------------------------------------------+--------------------------------------------------------+------------------+
; Node Name                                              ; Output Port Name                                       ; Output Port Type ;
+--------------------------------------------------------+--------------------------------------------------------+------------------+
; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result44w~0 ; |mux|lpm_mux:Mux0|mux_jcc:auto_generated|w_result44w~0 ; out0             ;
+--------------------------------------------------------+--------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon Nov 10 21:28:55 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off mux -c mux
Info: Using vector source file "D:/Program Files/quartus/Design/logic_design/mux/mux.vwf"
Info: Overwriting simulation input file with simulation results
    Info: A backup of mux.vwf called mux.sim_ori.vwf has been created in the db folder
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      95.65 %
Info: Number of transitions in simulation is 14377
Info: Vector file mux.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 84 megabytes of memory during processing
    Info: Processing ended: Mon Nov 10 21:28:56 2008
    Info: Elapsed time: 00:00:01