fcsr.v

来自「伪随机序列产生器－filtered 代进位反馈移位寄存器」· Verilog 代码 · 共 71 行

`timescale  1ns/1ns
 
     
 module fcsr    (clk, d, mkey, ckey, reset,load, mstate, cstate, mseq);
     

 parameter N = 3;        // Width of the shift register
 parameter T = 12;
 parameter  D= 7;
 
 
 input    clk;
 input   [N-1:0]   mkey;           
 input   [N-2:0]   ckey;
 input   [N-1:0]   d;
 input reset;
 input load;
 
 output   [N:0]  mstate;    
 output   [N-1:0]  cstate;
 output   [T-1:0]  mseq;
 
 
 reg      [N:0]  mstate;
 wire      [N:0]  mstate_N;  // Next state of the mainregister output
 reg      [N-1:0]  cstate;
 wire      [N:0]  cstate_N;  // Next state of the carries register output
 reg      [T-1:0]  mseq;
 
 reg [4:0] j;
 
 
 
 assign mstate_N[0]=mstate[1]^d[0]&cstate[0]^d[0]&mstate[0];
 assign mstate_N[1]=mstate[2]^d[1]&cstate[1]^d[1]&mstate[0];
 assign mstate_N[2]=mstate[3]^d[2]&cstate[2]^d[2]*mstate[0];
 assign mstate_N[3]=1'b0;
 assign cstate_N[0]=mstate[1]&cstate[0]^cstate[0]&mstate[0]^mstate[1]&mstate[0]; 
 assign cstate_N[1]=mstate[2]&cstate[1]^cstate[1]&mstate[0]^mstate[2]&mstate[0]; 
 assign cstate_N[2]=1'b0;
 
 always @(posedge clk) begin
   if(reset) begin
     j<=0;
     mstate<={1'b0, mkey[N-1:0]};
     cstate<={1'b0, ckey[N-2:0]};
     mseq<=0;
   end
   else if(load)begin
       j<=0;
       mstate<={1'b0, mseq[N-1:0]};
       cstate<={1'b0, ckey[N-2:0]};
       mseq<=0;
   end
   else begin
     if(j==12) begin
       j<=0;
     end
     else begin
       j<=j+1;
       mseq[j]<=mstate[0];
       mstate<=mstate_N;
       cstate<=cstate_N;
     end
   end
 end 
 endmodule