fcsr_test.v

来自「伪随机序列产生器－代进位反馈移位寄存器」· Verilog 代码 · 共 40 行

`timescale  1ns/1ns


module fcsr_test;
 

 reg   clk;
 
 parameter N=3;
 parameter T=12;
 
 wire      [N:0]  mstate;
 wire      [N-1:0]  cstate;
 reg      [N-1:0]  mkey;
 reg      [N-2:0]  ckey;
 reg      [N-1:0]    d;
 wire      [T-1:0]  mseq;
 reg reset;
 reg load;
 
 initial
   begin
      clk=0;
      d=3'b111;
      mkey=3'b1;
      ckey=2'b0;
      reset=1;
   #100 reset=0;
      load=0;
   #70  load=1;
   #20  load=0;
   end
    
    always #10 clk= ~clk;
 
 
 fcsr f1 (.clk(clk),  .d(d), .mkey(mkey), .ckey(ckey), .reset(reset), .load(load), .mstate(mstate), .cstate(cstate), .mseq(mseq));
 
    
 endmodule