alu.v

ALU设计实现

/**********************************************************************
 * Model of an ALU - Verilog Training Course.
 *********************************************************************/
`timescale 1ns / 100ps
module alu(alu_out, zero, opcode, data, accum);
  input [7:0] data, accum;
  input [2:0] opcode;
  output [7:0] alu_out;
  output zero;
  
  reg zero;   
  reg [7:0] alu_out;

  `define pass_accum  3'b000, 3'b001, 3'b110, 3'b111
  `define Add         3'b010
  `define And         3'b011
  `define Xor         3'b100
  `define pass_data   3'b101

  always @(accum)
    #1.2 zero = (!accum);

  always @(accum or data or opcode)
    #3.5 case (opcode)
      `Add         : alu_out = accum + data;
      `And         : alu_out = accum & data;
      `Xor         : alu_out = accum ^ data;
      `pass_data   : alu_out = data ;
      `pass_accum  : alu_out = accum;
      default      : alu_out = 8'bx; 
     endcase

endmodule