cd.fnsim.qmsg

一个彩灯循环控制的VHDL程序,功能还可添加.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 04 20:13:05 2008 " "Info: Processing started: Tue Nov 04 20:13:05 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cd -c cd --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cd -c cd --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "cd.vhd 2 1 " "Warning: Using design file cd.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cd-m " "Info: Found design unit 1: cd-m" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cd " "Info: Found entity 1: cd" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cd " "Info: Elaborating entity \"cd\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "jishu2 cd.vhd(24) " "Warning (10631): VHDL Process Statement warning at cd.vhd(24): inferring latch(es) for signal or variable \"jishu2\", which holds its previous value in one or more paths through the process" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 24 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dout_tmp cd.vhd(94) " "Warning (10492): VHDL Process Statement warning at cd.vhd(94): signal \"dout_tmp\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 94 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dout_tmp cd.vhd(34) " "Warning (10631): VHDL Process Statement warning at cd.vhd(34): inferring latch(es) for signal or variable \"dout_tmp\", which holds its previous value in one or more paths through the process" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dout_tmp\[0\] cd.vhd(34) " "Info (10041): Inferred latch for \"dout_tmp\[0\]\" at cd.vhd(34)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dout_tmp\[1\] cd.vhd(34) " "Info (10041): Inferred latch for \"dout_tmp\[1\]\" at cd.vhd(34)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dout_tmp\[2\] cd.vhd(34) " "Info (10041): Inferred latch for \"dout_tmp\[2\]\" at cd.vhd(34)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dout_tmp\[3\] cd.vhd(34) " "Info (10041): Inferred latch for \"dout_tmp\[3\]\" at cd.vhd(34)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dout_tmp\[4\] cd.vhd(34) " "Info (10041): Inferred latch for \"dout_tmp\[4\]\" at cd.vhd(34)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dout_tmp\[5\] cd.vhd(34) " "Info (10041): Inferred latch for \"dout_tmp\[5\]\" at cd.vhd(34)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dout_tmp\[6\] cd.vhd(34) " "Info (10041): Inferred latch for \"dout_tmp\[6\]\" at cd.vhd(34)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dout_tmp\[7\] cd.vhd(34) " "Info (10041): Inferred latch for \"dout_tmp\[7\]\" at cd.vhd(34)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "jishu2\[0\] cd.vhd(24) " "Info (10041): Inferred latch for \"jishu2\[0\]\" at cd.vhd(24)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 24 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "jishu2\[1\] cd.vhd(24) " "Info (10041): Inferred latch for \"jishu2\[1\]\" at cd.vhd(24)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 24 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "jishu2\[2\] cd.vhd(24) " "Info (10041): Inferred latch for \"jishu2\[2\]\" at cd.vhd(24)" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 24 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "10 " "Info: Inferred 10 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "d:/quartusii/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "d:/quartusii/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux0\"" {  } { { "cd.vhd" "Mux0" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux1\"" {  } { { "cd.vhd" "Mux1" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux2\"" {  } { { "cd.vhd" "Mux2" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux3\"" {  } { { "cd.vhd" "Mux3" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux4\"" {  } { { "cd.vhd" "Mux4" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux5\"" {  } { { "cd.vhd" "Mux5" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux6\"" {  } { { "cd.vhd" "Mux6" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux7 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux7\"" {  } { { "cd.vhd" "Mux7" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux8 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux8\"" {  } { { "cd.vhd" "Mux8" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartusii/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartusii/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/quartusii/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "d:/quartusii/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/quartusii/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}