cd.map.rpt

一个彩灯循环控制的VHDL程序,功能还可添加.

; Total logic elements                        ; 120       ;
;     -- Combinational with no register       ; 114       ;
;     -- Register only                        ; 4         ;
;     -- Combinational with a register        ; 2         ;
;                                             ;           ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 73        ;
;     -- 3 input functions                    ; 29        ;
;     -- 2 input functions                    ; 13        ;
;     -- 1 input functions                    ; 1         ;
;     -- 0 input functions                    ; 0         ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 115       ;
;     -- arithmetic mode                      ; 5         ;
;     -- qfbk mode                            ; 0         ;
;     -- register cascade mode                ; 0         ;
;     -- synchronous clear/load mode          ; 0         ;
;     -- asynchronous clear/load mode         ; 0         ;
;                                             ;           ;
; Total registers                             ; 6         ;
; Total logic cells in carry chains           ; 6         ;
; I/O pins                                    ; 9         ;
; Maximum fan-out node                        ; jishu1[1] ;
; Maximum fan-out                             ; 37        ;
; Total fan-out                               ; 424       ;
; Average fan-out                             ; 3.29      ;
+---------------------------------------------+-----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |cd                        ; 120 (120)   ; 6            ; 0           ; 9    ; 0            ; 114 (114)    ; 4 (4)             ; 2 (2)            ; 6 (6)           ; 0 (0)      ; |cd                 ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; dout_tmp[0]                                         ; Mux8                ; yes                    ;
; dout_tmp[1]                                         ; Mux8                ; yes                    ;
; dout_tmp[2]                                         ; Mux8                ; yes                    ;
; dout_tmp[3]                                         ; Mux8                ; yes                    ;
; dout_tmp[4]                                         ; Mux8                ; yes                    ;
; dout_tmp[5]                                         ; Mux8                ; yes                    ;
; dout_tmp[6]                                         ; Mux8                ; yes                    ;
; dout_tmp[7]                                         ; Mux8                ; yes                    ;
; jishu2[2]                                           ; GND                 ; yes                    ;
; jishu2[0]                                           ; GND                 ; yes                    ;
; jishu2[1]                                           ; GND                 ; yes                    ;
; Number of user-specified and inferred latches = 11  ;                     ;                        ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 6     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |cd|jishu2[2]~3            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Nov 04 20:10:52 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cd -c cd
Warning: Using design file cd.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: cd-m
    Info: Found entity 1: cd
Info: Elaborating entity "cd" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at cd.vhd(24): inferring latch(es) for signal or variable "jishu2", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at cd.vhd(94): signal "dout_tmp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at cd.vhd(34): inferring latch(es) for signal or variable "dout_tmp", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "dout_tmp[0]" at cd.vhd(34)
Info (10041): Inferred latch for "dout_tmp[1]" at cd.vhd(34)
Info (10041): Inferred latch for "dout_tmp[2]" at cd.vhd(34)
Info (10041): Inferred latch for "dout_tmp[3]" at cd.vhd(34)
Info (10041): Inferred latch for "dout_tmp[4]" at cd.vhd(34)
Info (10041): Inferred latch for "dout_tmp[5]" at cd.vhd(34)
Info (10041): Inferred latch for "dout_tmp[6]" at cd.vhd(34)
Info (10041): Inferred latch for "dout_tmp[7]" at cd.vhd(34)
Info (10041): Inferred latch for "jishu2[0]" at cd.vhd(24)
Info (10041): Inferred latch for "jishu2[1]" at cd.vhd(24)
Info (10041): Inferred latch for "jishu2[2]" at cd.vhd(24)
Warning: Latch dout_tmp[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal jishu2[1]
Warning: Latch dout_tmp[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal jishu2[2]
Warning: Latch dout_tmp[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal jishu2[2]
Warning: Latch dout_tmp[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal jishu2[2]
Warning: Latch dout_tmp[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal jishu2[2]
Warning: Latch dout_tmp[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal jishu2[2]
Warning: Latch dout_tmp[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal jishu2[2]
Warning: Latch dout_tmp[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal jishu2[2]
Info: Implemented 129 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 8 output pins
    Info: Implemented 120 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
    Info: Allocated 156 megabytes of memory during processing
    Info: Processing ended: Tue Nov 04 20:11:00 2008
    Info: Elapsed time: 00:00:08