prev_cmp_zhiliu_dianji.tan.qmsg

直流电机的VHDL源程序,经过编译和仿真.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Web Edition " "Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 21 00:46:37 2007 " "Info: Processing started: Fri Dec 21 00:46:37 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off zhiliu_dianji -c zhiliu_dianji --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off zhiliu_dianji -c zhiliu_dianji --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "d\[3\] w_pwm 9.824 ns Longest " "Info: Longest tpd from source pin \"d\[3\]\" to destination pin \"w_pwm\" is 9.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns d\[3\] 1 PIN PIN_61 2 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_61; Fanout = 2; PIN Node = 'd\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[3] } "NODE_NAME" } } { "comp.vhd" "" { Text "E:/zhiliu_dianji/comp.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.026 ns) + CELL(0.434 ns) 6.595 ns LessThan0~82 2 COMB LC_X1_Y19_N3 1 " "Info: 2: + IC(5.026 ns) + CELL(0.434 ns) = 6.595 ns; Loc. = LC_X1_Y19_N3; Fanout = 1; COMB Node = 'LessThan0~82'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.460 ns" { d[3] LessThan0~82 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.137 ns) 6.732 ns LessThan0~77 3 COMB LC_X1_Y19_N4 1 " "Info: 3: + IC(0.000 ns) + CELL(0.137 ns) = 6.732 ns; Loc. = LC_X1_Y19_N4; Fanout = 1; COMB Node = 'LessThan0~77'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.137 ns" { LessThan0~82 LessThan0~77 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.478 ns) 7.210 ns LessThan0~50 4 COMB LC_X1_Y19_N9 1 " "Info: 4: + IC(0.000 ns) + CELL(0.478 ns) = 7.210 ns; Loc. = LC_X1_Y19_N9; Fanout = 1; COMB Node = 'LessThan0~50'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.478 ns" { LessThan0~77 LessThan0~50 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(1.622 ns) 9.824 ns w_pwm 5 PIN PIN_239 0 " "Info: 5: + IC(0.992 ns) + CELL(1.622 ns) = 9.824 ns; Loc. = PIN_239; Fanout = 0; PIN Node = 'w_pwm'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { LessThan0~50 w_pwm } "NODE_NAME" } } { "comp.vhd" "" { Text "E:/zhiliu_dianji/comp.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.806 ns ( 38.74 % ) " "Info: Total cell delay = 3.806 ns ( 38.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.018 ns ( 61.26 % ) " "Info: Total interconnect delay = 6.018 ns ( 61.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.824 ns" { d[3] LessThan0~82 LessThan0~77 LessThan0~50 w_pwm } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.824 ns" { d[3] {} d[3]~out0 {} LessThan0~82 {} LessThan0~77 {} LessThan0~50 {} w_pwm {} } { 0.000ns 0.000ns 5.026ns 0.000ns 0.000ns 0.992ns } { 0.000ns 1.135ns 0.434ns 0.137ns 0.478ns 1.622ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 21 00:46:40 2007 " "Info: Processing ended: Fri Dec 21 00:46:40 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}