alt_u_div_8re.tdf

直流电机的VHDL源程序,经过编译和仿真.

	add_sub_29 : add_sub_bdc;
	add_sub_3 : add_sub_6dc;
	add_sub_30 : add_sub_bdc;
	add_sub_31 : add_sub_bdc;
	add_sub_4 : add_sub_7dc;
	add_sub_5 : add_sub_8dc;
	add_sub_6 : add_sub_9dc;
	add_sub_7 : add_sub_adc;
	add_sub_8 : add_sub_bdc;
	add_sub_9 : add_sub_bdc;
	DenominatorIn[296..0]	: WIRE;
	DenominatorIn_tmp[296..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[1055..0]	: WIRE;
	NumeratorIn[1055..0]	: WIRE;
	NumeratorIn_tmp[1055..0]	: WIRE;
	prestg[287..0]	: WIRE;
	quotient_tmp[31..0]	: WIRE;
	sel[263..0]	: WIRE;
	selnose[1055..0]	: WIRE;
	StageIn[296..0]	: WIRE;
	StageIn_tmp[296..0]	: WIRE;
	StageOut[287..0]	: WIRE;

BEGIN 
	add_sub_0.dataa[0..0] = NumeratorIn[31..31];
	add_sub_0.datab[0..0] = DenominatorIn[0..0];
	add_sub_1.dataa[] = ( StageIn[9..9], NumeratorIn[62..62]);
	add_sub_1.datab[1..0] = DenominatorIn[10..9];
	add_sub_10.dataa[] = ( StageIn[97..90], NumeratorIn[341..341]);
	add_sub_10.datab[8..0] = DenominatorIn[98..90];
	add_sub_11.dataa[] = ( StageIn[106..99], NumeratorIn[372..372]);
	add_sub_11.datab[8..0] = DenominatorIn[107..99];
	add_sub_12.dataa[] = ( StageIn[115..108], NumeratorIn[403..403]);
	add_sub_12.datab[8..0] = DenominatorIn[116..108];