alt_u_div_8re.tdf

直流电机的VHDL源程序,经过编译和仿真.

FUNCTION add_sub_adc (dataa[7..0], datab[7..0])
RETURNS ( cout, result[7..0]);

--synthesis_resources = lut 231 
SUBDESIGN alt_u_div_8re
( 
	den_out[7..0]	:	output;
	denominator[7..0]	:	input;
	numerator[31..0]	:	input;
	quotient[31..0]	:	output;
	remainder[7..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_3dc;
	add_sub_1 : add_sub_4dc;
	add_sub_10 : add_sub_bdc;
	add_sub_11 : add_sub_bdc;
	add_sub_12 : add_sub_bdc;
	add_sub_13 : add_sub_bdc;
	add_sub_14 : add_sub_bdc;
	add_sub_15 : add_sub_bdc;
	add_sub_16 : add_sub_bdc;
	add_sub_17 : add_sub_bdc;
	add_sub_18 : add_sub_bdc;
	add_sub_19 : add_sub_bdc;
	add_sub_2 : add_sub_5dc;
	add_sub_20 : add_sub_bdc;
	add_sub_21 : add_sub_bdc;
	add_sub_22 : add_sub_bdc;
	add_sub_23 : add_sub_bdc;
	add_sub_24 : add_sub_bdc;
	add_sub_25 : add_sub_bdc;
	add_sub_26 : add_sub_bdc;
	add_sub_27 : add_sub_bdc;
	add_sub_28 : add_sub_bdc;