tri_s8.vhd

来自「双口RAM与PXI总线接口设计」· VHDL 代码 · 共 15 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_s8 IS
port ( endata4 :IN STD_LOGIC;
	idata365 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	odata365 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END  tri_s8;
ARCHITECTURE bhv OF tri_s8 IS
BEGIN
PROCESS(endata4,idata365)
BEGIN
IF endata4 = '1' THEN odata365 <= idata365 ;
ELSE odata365 <="ZZZZZZZZ" ; END IF ;
END PROCESS;
END bhv;